Role of ICs in Green IT

Laura Peters, Lead Technical Editor -- Semiconductor International, 11/8/2007 7:19:00 AM

The rapidly rising consumption of electricity and the demands of international communication mean that beyond 2010, electricity costs, including cooling, could require the same amount of capital investment as the servers themselves. Summarized another way, if the increase of internet activity continues at its current pace, power used by routers could occupy ~10% of the total power consumed in Japan in 2015. The rising toll of power consumption was one of the metrics that Michiharu Nakamura, Fellow at Hitachi Ltd. (Tokyo) examined in his talk on the role of semiconductor manufacturing in Green IT, presented at the International Trade Partners Conference (ITPC), a SEMI (San Jose) event held in Maui earlier this week. Nakamura discussed various global efforts designed to improve the energy efficiency in data centers and pointed to ways that IC design and fabrication will directly influence this energy efficiency.

Japan’s Green IT Project aims to reduce the power consumption of IT equipment by 40% in 2025. This power savings (~100 BkWh) is equivalent to a CO₂ emission reduction of 55 million tons — the amount produced by heaters from household in Japan per year. At the system, equipment and chip levels, this comes down to implementing low-power data centers, networks, displays and devices. More specifically, heterocore architectures, ultralow-power transistors, highly efficient power supplies, optical switches, optical interconnects and 3-D system-in-a-package (SiP) approaches should all play a role in reducing power consumption at the chip level.

The concept of multicore processors will be taken to the next level — heterogeneous chip multiprocessors (embedding general processors with application-specific processors on a chip) — to achieve improved performance with superior power efficiency. The next-generation non-volatile memory (NVM) solution, which is greatly debated in the industry, will require a system-on-a-chip (SOC) compatible design. Nakamura suggested that the spin-transfer torque RAM is a likely contender. In terms of 3-D integration, he outlined the major challenges of 3-D SiP, including manufacturing issues such as achieving submicron alignment accuracy, thin wafer processing, yield, reliability and thermal management, as well as electronic design issues, including tool support for 3-D design/verification, electromagnetic interference (EMI) effects, simulation and thermal analysis. Importantly, he pointed out the need to be able to determine when 3-D approaches are more cost-effective than 2-D SoCs.

A move to silicon on insulator (SOI) substrates for dual-gate field-effect transistors (FETs) is one way to address threshold voltage (V_t) variability at shrinking device dimensions and low V_dd. Nakamura noted that mobility enhancement in channels will continue to deliver improved performance, and 3-D structures, such as the finFET, surrounding gate transistors or silicon nanowires, will help suppress short-channel effects. He provided the example of an optical interconnect integrated on an LSI chip. The optical interconnect uses a silicon nano-photodiode (Figure), SiON optical waveguide and PLZT optical modulator.

The silicon nano-photodiode could provide the interface between the chip and board-level optical interconnects.