Grose Considers High-k, SOI, 300mmPrime
David Lammers, News Editor -- Semiconductor International, 11/6/2007 9:33:00 AM
Doug Grose, senior vice president of manufacturing and supply chain management at Advanced Micro Devices Inc. (Sunnyvale, Calif.), has been in the proverbial hot seat ever since he left IBM Corp. (White Plains, N.Y.) to join AMD in early February. Just 10 days before he settled into his new job, Intel Corp. (Santa Clara, Calif.) surprised many by announcing that it would bring high-k/metal gate technology to its 45 nm production lines.
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| Doug Grose, Senior Vice President, AMD. |
AMD, Grose said, “has developed a high-k/metal gate capability focused on 32 nm, and it has gone well. We absolutely are working on plans to have it available on our 45 nm process, in the latter portion of some of those product lifecycles. It is not just having the technology, but applying it to a product, to have them come together. We can demonstrate [high-k/metal gate] on 45, and have it available as we need it.”
At an AMD analysts meeting in Sunnyvale this summer, Grose said that AMD was studying its silicon on insulator (SOI) vs. bulk options. The company plans to do some future price-sensitive products in bulk silicon, while other high-performance MPUs will remain on SOI substrates.
“Our world got much more interesting when we acquired ATI,” Grose said. All of the products that the classic ATI had developed and produced use bulk silicon and are made at foundries, with Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) as the major base.
“SOI gives us an advantage. Transistor performance is the name of the game in CPUs. Where you are trading off pure performance and power, there is an advantage that SOI gives us. The joint development work with IBM, which is continuing in New York, is all SOI-based, and we are continuing that work.
“However, when we do look at some future products, with our Fusion product line, we are combining aspects of the graphics processors with the CPUs and other elements. By having both the bulk and SOI technologies available to us, we are really letting the product applications and needs dictate whether those products are on an SOI base or in bulk. We have both capabilities available. The decisions are driven by product needs and by the reuse of the IP. The IP that is developed in SOI makes a whole lot of sense to stay on SOI if it’s a performance- or power-based product,” he said.
Beyond 32 nm, Grose said AMD remains open-minded about SOI. “Any time you are in the research phase of a new technology, there are choices, and that is what the R&D teams are looking at. There are choices we have not made with our partners about any one road we may go down. Our experience base with SOI, which drives power performance, that experience base is huge. From that standpoint, we are looking at a number of elements we have to narrow down as we move to the 22 nm time frame.”
Recently, Grose, who has a doctorate in materials science from Rensselaer Polytechnic Institute (Troy, N.Y.), has become a vocal leader of the 300mmPrime initiative, as evidenced by a keynote speech at the recent International Sematech Manufacturing Initiative (ISMI, Austin, Texas) manufacturing symposium.
Also, Grose is supporting an initiative by AMD and its suppliers to test out ideas at an AMD Advanced Development Center now being built in central Austin. Grose said his ISMI keynote speech resulted in messages of support from major equipment suppliers, including an email from one of the leading equipment CEOs saying that the 300mmPrime program is “exactly the right thing for the industry.”
"We think there is a lot more to be gotten out of 300 mm, and that’s where the investment needs to be. There is a pretty good consensus from the supply base about that. There is a time and a place where improvements will apply to 450 mm, and we need a coordinated approach where that long investment cycle starts. The equipment vendors have a long investment return cycle when they do go down the road to the 450 mm wafer size. The industry only has so many resources, and we believe 300mmPrime is the best way to get the cost of silicon down in the most efficient manner.”
With companies such as AMD, IBM and others championing the 300mmPrime initiative, and others such as Intel Corp. favoring a strong push in the 450 mm direction, Grose was asked if the semiconductor industry is pulling in different directions. “The divisions are more intense, and there is a little bit less cooperation, a little bit less dialogue than is needed. Obviously, we at AMD keep influencing as much as we can where those investments are going. Our resources are not unlimited and investments have to be prioritized so that it is not just one or two companies, but a coordinated effort, where the suppliers are putting their investments,” he said.
Grose added that the AMD Advanced Development Center is part of an effort to “make sure the industry focuses on 300mmPrime. The focus for AMD is to get as much leverage as we can get by exploring smaller batch sizes. There are issues that have to be worked through when it comes to automation and front-end interfaces. We want to work through that with the equipment suppliers, and they have expressed an interest to work with us. We want to get others to work with us, so we can get the data.
“There is only so much we can do at our own production lines in Dresden when it comes to advanced precison manufacturing control improvements, including the algorithms and software. The development center came about because AMD needed a place offline to prove out other validation work. It is driven by us and our needs,” he said.
While the 25-wafer FOUP dominates, SEMI (San Jose) did develop a standard for a 13-wafer FOUP that never caught on. Grose said AMD has data that indicates that stepping down the lot size shows a benefit in the queuing time at the tools.
The Advanced Development Center will study smaller lots from two perspectives, the batch tools that have been driven by the larger batch sizes, and the single wafer tools (SWTs), which are increasingly employed. Grose said AMD is studying the advantages of taking 25 wafer lot sizes down to 12, and then six wafers, and then one.
“There are improvements, but you run into other problems you have to work through. A lot of it is the interface. How do you stage the wafers, to achieve the correct front-end elements to some of the tools? There are automation aspects. We think there is promise to single wafer processes, and there are proof points that that is directionally correct.”
The 12-wafer lots are used now to improve speed in the manufacturing line, accelerate the introduction of new products, and validate product changes.
“Speed has a lot of attributes,” Grose said, including fewer wafers waiting around, less waste amd fewer defects, which result in higher yields. "With a change in your cycle time, you get a one-time benefit the first time you do it, and then everything in the line moves at a faster speed. You are discovering issues faster. Manufacturing and characterization become a lot more efficient across the board.
“The challenge is, ‘How do you manage very different automation and interface requirements?’ We have to get to the right balance point, and a lot of data has yet to be gathered.”
Lead photo courtesy of Sven Doring, Advanced Micro Devices Inc.
