'Big Four' Talking 450 With Tool Vendors
David Lammers, News Editor -- Semiconductor International, 10/30/2007 8:06:00 AM
Proponents of the 450 mm wafer generation said they are in discussions with equipment vendors to create a business model that will entice toolmakers to put their own skin in the high stakes 450 mm wafer game.
Tom Abell, 450 mm program manager at the International Sematech Manufacturing Initiative (ISMI, Austin, Texas) and an Intel (Santa Clara, Calif.) assignee to the 16-member ISMI consortium, said the four largest chip companies in support of the 450 mm standard — Intel Corp., Samsung Electronics Co., Toshiba Corp. and Taiwan Semiconductor Manufacturing Corp. (TSMC, Hsinchu, Taiwan) — are in discussions with equipment suppliers about ways to create a consortia-like approach to 450 mm equipment development.
In the third quarter of this year, according to IC Insights (Scottsdale, Ariz.), those four IC makers accounted for ~$21B in chip revenues, out of ~$35B total in the quarter. Despite that clout, the largest equipment vendors, including Applied Materials Inc. (Santa Clara, Calif.), have largely opposed the International Technology Roadmap for Semiconductors (ITRS) call for insertion of the 450 mm wafers starting in 2012.
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| Tom Abell, ISMI 450 mm program manager |
For the 450 mm generation, “A third way needs to be developed. The devicemakers are looking at the cost model and trying to figure out, ‘How can we provide support?’ Discussions are occurring, talks about risk sharing. There are a number of ways that we could do it,” Abell said.
“We need to maintain close links with the suppliers so there are no mixed signals,” he said. By working together, the industry can get “the most efficient use of its R&D, in a forward-compatible approach, so both the devicemakers and the suppliers receive benefits. Otherwise, the economics of it don’t work out,” Abell said.
Wafer thickness standard important
For the 450 mm programs, standards for the wafer carriers are a top priority. Improved standards are needed for the shipping carriers, which bring the 450 mm wafers from the silicon wafer manufacturers to the fabs.
“We need all-automated handling from the shippers to the carriers, as the wafers come into shipping and receiving. The transfer into the FOUP has to happen in an automated fashion,” Abell said.
A standard for the thickness of the 450 mm wafers is needed soon, partly because the thickness determines the design of the front-opening universal pods (FOUPs) and other wafer-handling and storage standards.
“A whole set of things follow from the thickness,” Abell told the ISMI symposium participants.
Mike Goldstein, an Intel material scientist working on 450 mm wafer development, said if the proposed 825 µm thickness for the 450 mm wafer standard remains in place, it would result in unacceptable levels of sag. Goldstein said he is proposing a 925 µm thickness, a significant increase from the 775 µm thickness used for the 300 mm wafers.
“If it is too thick, the wafers become too expensive and too heavy,” he said. A 925-µm-thick wafer would weigh about 340 grams, he estimated, noting that a pound equals 440 grams.
The major silicon vendors working on 450 mm development have created “nice crystals up to 300 kg,” he said, adding that the production-use ingots will weigh in the range of 700-800 kg.
“There are a lot of challenges at this point. The biggest is how to create a perfect crystal,” Goldstein said.
Wafer test bed needed
ISMI plans to build a wafer-handling test bed next year involving companies making the FOUPs, robotics, wafer handlers, track and other companies involved in wafer handling, he said. ISMI is considering building a test piece of mainframe process equipment, with the standard equipment front-end modules (EFEM) interface, said Joe Draina, associate director of ISMI and an IBM Corp. (Yorktown Heights, N.Y.) assignee to the consortium.
The test bed will use sintered silicon wafers, made from a silicon powder that is placed under pressure, then sliced into the same shape, thickness and weight as the later single-crystal wafers.
“The sintered wafers will have very similar optical and mechanical properties to the single crystal wafers, but at a cost that is significantly lower,” Abell said, adding that he expects the major silicon wafer manufacturers to deliver single-crystal silicon by the second half of next year.
The wafer-handling test bed is needed to overcome problems that became clear in the development of the 300 mm generation. Then, standards were developed, but the physical testing was insufficient to ensure that each FOUP manufacturer, for example, created interoperable boxes.
“We need to make sure that each FOUP handles the wafer the same way,” Abell said, with FOUPs from different manufacturers able to enter every load port, with full interoperability.
“With the 300 mm generation, we set the standards too early and then changed them later,” he added.
One goal of the wafer-handling test bed will be improved automation, with automated ability to open the FOUP, remove the wafer and manipulate the wafer into a piece of equipment. “Eventually, we want to orient the robot to return the wafer into the FOUP, but not necessarily the same FOUP or the same slot,” he said.
At the upcoming SEMICON Japan show planned for Dec. 5-7, discussions will continue about how the 450 mm handlers can best meet the needs of both the low- and high-mix manufacturers (i.e., those with many diverse products running through the fab vs. those that run in higher volumes).
