Memories of the Future

Floating-gate NAND flash remains the dominant technology in the rapidly growing non-volatile memory (NVM) market. There is general agreement, however, that with continued scaling on a pace of 2×/year, fundamental barriers will soon be reached.

While work continues (of course) on extending existing technology through the use of multilevel schemes, which enable the storage of two bits in one physical cell by programming to four different levels, interesting advancements in alternative technologies have been made. One of the most promising (and likely successor) is charge trapping in nanocrystalline and nitride-based layers. Silicon/oxide/nitride/oxide/silicon (SONOS) is a good example of the latter (see “SONOS Eases Non-Volatile Memory Integration in SoC”).

Another interesting option is phase-change memory (PCM), which is a resistor-based memory where the resistor is made of a chalcogenide material. By means of Joule heating, the material can be either molten and successively quenched in a high-resistive amorphous phase, or heated to below the melting point to induce transformation to the low-resistive crystalline phase.

PCM is promising because material changes are unnecessary and no physical limits are foreseen down to ~5 nm over the next decade. At a recent Applied Materials-sponsored panel, presenters agreed that PCM is attractive in its cell size, die size and cost. It offers ~50 nsec read performance, has unlimited read endurance, ~10-year data retention, ~100 nsec write performance, and is CMOS compatible. It exceeds current flash technology in terms of its bit-level write capabilities, requires no erasing before writing, and has a ~10⁸ cycles of write endurance.

South Korean memory giant Hynix Semiconductor Inc. also appears to see potential in PCM. The company recently signed a long-term license agreement with Rochester Hills, Mich.-based phase-change semiconductor memory technology developer Ovonyx Inc.

Ferroelectric RAM (FeRAM), magnetic RAM (MRAM) and new resistive-switching concepts also have potential as the eventual successor to NAND flash.

Papers on these and other NVM technology are scheduled to be presented at the upcoming International Electron Devices Meeting (IEDM) next month in Washington, D.C.

Among the more interesting of these papers is work done by Toshiba (Tokyo) on 3-D architectures, which are being increasingly investigated for future cost-effective ultrahigh-density memories. Toshiba researchers will describe an approach they call bit-cost-scalable (BiCS) flash technology. The basic idea is that a stack of electrode plates are punched through all at once and plugged with polysilicon, forming a series of vertical field-effect transistors (FETs) that act as a NAND string of SONOS-type memories.

Toshiba researchers describe how the polysilicon body needs to be much thinner than the depletion width to achieve good threshold voltage (V_t) control. To accomplish this, a very thin layer of polysilicon was deposited on a SiN gate dielectric that lined the holes in the stack of electrode plates. The polysilicon formed a hollow macaroni-shaped body. Its hollow center (Figure) was filled with dielectric to make process integration easier. The device's work was performed in depletion-mode, with the body polysilicon undoped or lightly n-doped uniformly, to avoid having to form p-n junctions within the plug. Each electrode plate acts as a control gate except for the lowest plate, which functions as the lower select gate. A single bit is accessed at the intersection of a control gate plate and a string, which is selected by a bit line and an upper select gate. The bottom of the memory string is connected to the common source diffusion formed on the silicon substrate. The researchers will discuss a novel 4F² cell array structure that can lead to lower bit costs, and they said the macaroni body design offers better controllability until ~30 nm.

This ‘macaroni’ body vertical field-effect transistor (FET) was used in a novel 4F2 cell array structure that can lead to lower bit costs, according to the researchers who developed the technology. (Source: Toshiba)

In other work scheduled to be presented, Toshiba and SanDisk (Milpitas, Calif.) will describe how they were able to thin the intergate dielectric, which is situated between the floating and control gates, to <13 nm, a world's first.

Macronix (Hsinchu, Taiwan) researchers will describe a new method to program and erase NAND devices without using high-voltage Fowler-Nordheim (FN) stressing for SONOS-type NAND flash memories. Instead, they relied on impact ionization-generated substrate hot electron (IIHE) and band-to-band tunneling hot hole (BBHH) techniques. Both junctions are biased with the same voltage to perform double-side charge injection without lateral electrical field-induced current. A novel divided bit line architecture is introduced to achieve this operation.

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