SONOS Eases Non-Volatile Memory Integration in SoC

System-on-a-chip (SoC) sounds like a simple concept: Take a slab of silicon, throw in a microprocessor, add some I/O and memory, maybe a pinch of analog, and mix well.

But making it a reality is not so simple. The main problem is that each of these circuit blocks has its own unique processing requirements. The standard CMOS logic used in the microprocessor needs good step coverage, the dense circuitry used in RAM demands tight spacing, and the multiple resistors used in analog circuits require well-controlled implants. Designing a process to meet all these needs can be an incredibly tricky balancing act.

Problems with floating gate

Non-volatile memory (NVM) is quickly becoming a “must-have” function for SoC. System designers depend on NVM to store critical information that must be maintained through a power outage, such as the programming code for the microprocessor. However, NVM can be one of the most difficult circuit blocks to integrate into a standard CMOS manufacturing process.

Today, the NVM technology most commonly used in SoC is the floating gate. Floating gate has many advantages. It has been around for over four decades, making it a well-understood technology. It's relatively dense, in that it can provide a lot of memory in a small space. And its high programming currents give it fast programming speeds.

But this technology has some drawbacks as well — drawbacks that make it difficult to integrate onto a SoC. Its high stack height makes step coverage a challenge, and can result in thinned or broken metal lines and open contacts. The oxide that insulates the floating gate from the channel is susceptible to pinholes, which can render the device inoperable. Floating gate devices require additional mask and processing steps, which increase manufacturing time and costs and can have a detrimental effect on the other circuitry in the SoC. Because of electrical interference between adjacent cells, floating gate is expected to reach its scaling limit between the 22 and 45 nm process nodes.¹ This means that floating gate will not be able to deliver the memory-hungry products of the future, such as virtual reality devices and real-time language translators.

SONOS to the rescue

Silicon/oxide/nitride/oxide/silicon (SONOS) is a memory technology that provides most of the advantages of floating gate without any of its disadvantages. It differs from floating gate in that the electrons used to store the data are distributed throughout a thin insulating layer of silicon nitride (Si₃N₄) rather than concentrated on a thick conducting layer of polysilicon. Figure 1 depicts a comparison of the cross-section of the cells.

1. The stack height of floating gate can be twice the stacking of SONOS, primarily caused by the difference in the thickness of the storage layer.

SONOS is an often-misunderstood technology. Some think of it as an old technology first introduced in the 1960s and then abandoned as being unmanufacturable. Others view it as a futuristic technology that is not yet practical for real-world applications.

In fact, SONOS-based memories have been in production for over 20 years and, while they have not been manufactured in the volumes of floating gate memories, they have routinely outperformed them in niche applications where reliability and high-temperature operation are critical. And recent improvements in the technology have made SONOS a formidable competitor to floating gate in commercial-grade applications as well, with the latest SONOS devices offering faster read times, longer data retention and a significantly greater number of read/write cycles. Most importantly, SONOS doesn't have the scaling limitations of floating gate, so it may very well become the NVM of choice for the advanced applications of the future.

Embedding SONOS

SONOS lends itself particularly well to integration onto a SoC. This is because of four important process-related advantages: a low stack height, an insulating storage layer, simple processing, and excellent scalability.

Stack height, that is, the total height of the layers used to build the memory structure, is a critical parameter, as it defines the height of the step that the metal lines must cover. If the step is too high, the metal may become thinned, resulting in breakage and possible failure of the device. Step coverage is an issue particularly at the source/drain contacts. Poor step coverage here can result in electrically open contacts and, again, failure of the device.

Floating gate stacks can be twice as thick as SONOS stacks. A typical floating gate stack is 3400 Å, consisting of 100 Å of tunnel oxide, 1500 Å of floating gate, 300 Å of blocking oxide and 1500 Å of control gate. A typical SONOS stack, on the other hand, is only 1700 Å (Fig. 1). This consists of 20 Å of tunnel oxide, 60 Å of nitride, 30 Å of blocking oxide and 1500 Å of control gate. Note that this is comparable to the thickness of a CMOS transistor.

The difference in stack heights is primarily caused by the storage layers. The polysilicon used in floating gate must be deposited fairly thick to provide an acceptable coupling ratio between the floating gate and control gate. This coupling ratio does not apply in SONOS, so there is not the same limitation on the nitride thickness.

Tunnel oxide also contributes to the difference. In SONOS, this can be made much thinner because the charge transfer mechanism doesn't require as high a voltage, which will be discussed later in this article.

The material used in the storage layer is also a key consideration. Floating gate technology stores the charge on a conductive layer that is separated from the channel by a thin tunnel oxide. Any pinhole in this oxide will provide a direct short between the gate and channel, causing immediate and catastrophic charge loss (Fig. 2). Another concern is that repeated program/erase cycles on the memory cell will strain this oxide, eventually causing a destructive breakdown of the oxide and a similarly catastrophic loss of charge. This type of failure is unpredictable and cannot be screened at test.

2. In floating gate, pinholes in the tunnel oxide provide a direct short between the conducting gate and channel. In SONOS, pinholes only affect electrons that lie directly along their path.

The nitride layer used to store the charge in SONOS provides ironclad protection from these problems. Pinholes may still occur, but they will only discharge electrons lying directly along their path — a negligible fraction of the total charge stored within the nitride. More importantly, silicon nitride does not break down like oxide. Program/erase cycling causes only a gradual decay in the number of charges stored, not an immediate loss of all stored charges. This decay is easily measurable and can be successfully screened at the wafer-probe level, eliminating the risk of future failure.

Process complexity and the resulting interactions among the various manufacturing steps can be a major headache for process engineers. SONOS beats floating gate here as well. Compared with the standard CMOS process, floating gate adds two poly gates, two oxides (one tunnel oxide, one thick oxide for the high-voltage pump circuits) and up to 10 masking steps. This substantially increases cycle time and manufacturing costs. It can also adversely affect devices on the rest of the SoC. SONOS has much less of an effect because it adds only one poly gate, one (unpatterned) nitride, one oxide (pump voltages are lower) and three masking steps.

A final consideration is scaling, as this determines the future lifespan of the technology. Scaling of the floating gate is limited in the vertical direction because of the tunnel oxide. Fowler-Nordheim tunneling, which is used to erase the cell, requires relatively high voltages (17 V is typical), and these can damage the tunnel oxide. To protect against this, the tunnel oxide must be grown relatively thick. The lower limit on this thickness is around 100 Å. SONOS, on the other hand, uses direct tunneling to erase the cell. Voltages used in this technique are around 10 V, so they are much less damaging to the tunnel oxide. As a result, the lower limit on the tunnel oxide thickness is only 20 Å in SONOS.

Scaling of the floating gate is also limited in the lateral (gate-to-gate) direction. Electrons stored on the polysilicon gate exert an electric field on adjacent gates. As the geometry shrinks, this electric field becomes increasingly stronger. Eventually, the field can become so strong that it unintentionally programs or erases adjacent cells. This is the main reason floating gate technology is expected to hit a scaling limit at a channel length between 25 and 45 nm. We are not far from this limit today. The 45 nm process node is currently under development at a number of leading chip manufacturers, and many of them are expected to go into production with it in 2008.²

In SONOS, the charges are electrically trapped in the nitride so that they don't interfere with adjacent cells. Scaling always presents challenges, of course, but as of today, there are no known physical limits to the scaling of SONOS devices. The Table summarizes the process differences.

Alternatives to SONOS

SONOS is not the only alternative to floating gate technology. Recent developments have brought more exotic technologies into the limelight, including ferroelectrics (FRAM), magnetoresistive memories (MRAM) and phase-change memories (PCM).³ However, these technologies are still quite new and present a number of serious manufacturing hurdles. They also require unusual materials and processing equipment, adding significant costs to the manufacturing process. SONOS, on the other hand, uses materials that are readily available in any wafer fab, and the silicon nitride layer used to store the data can be deposited using standard processing equipment.

Conclusion

NVM is becoming increasingly important in SoC applications. Combining it with other circuit blocks, however, can pose significant problems for the process engineer. SONOS provides an elegant solution to these problems by providing a fast and reliable memory cell that can be easily integrated into existing manufacturing flows.