Toshiba Validates Imprint Lithography for <32 nm
Aaron Hand, Executive Editor, Electronic Media -- Semiconductor International, 10/16/2007 4:30:00 AM
Molecular Imprints Inc. (MII, Austin, Texas) today announced that Toshiba Semiconductor Co. (Tokyo) has validated the use of MII’s imprint lithography technology for 22 nm node CMOS devices.
Using MII’s Imprio 250 system, the memory manufacturer was able to print 18 nm isolated features and 24 nm dense features with <1 nm critical dimension uniformity (CDU) and <2 nm line edge roughness (LER). The Toshiba demonstrations also showed improved defectivity and overlay results for imprint lithography. Defectivity levels of as low as <0.3 defects per cm2 are approaching those of immersion lithography, and device overlay results were also within Toshiba’s required specifications. “It’s a very clear demonstration that we’ve got lithographic capability for 32 nm and below,” said Mark Melliar-Smith, MII’s CEO.
MII’s first Imprio step-and-repeat tool was unloaded on Toshiba’s docks near the beginning of this year, with acceptance coming in before the end of March. Toshiba presented these results last month at the International Conference on Micro- and Nano-Engineering (MNE) in Copenhagen, Denmark. “I think that’s really a pretty creditable schedule for the first tool of a very complicated lithographic technology,” Melliar-Smith said.
To Melliar-Smith, the speed of results illustrates a couple key factors of MII’s Step and Flash Imprint Lithography (S-FIL) technology: the facile nature of the technology, and how well it is supported by the industry infrastructure. “People look at us as being kind of out in left field, which really isn’t the case,” he said.
All of the imprint templates that Toshiba used for its imprint demonstrations were made by Dai Nippon Printing (DNP) using standard photomask technologies run at finer dimensions, according to Melliar-Smith. Another area of consistency with the current optical infrastructure is the ability to etch the wafers after they’ve been patterned.
“Our customers were pretty adamant that they wanted to make sure this technology was essentially a drop-in replacement for photolithography. You didn’t have to change any of the processing upstream or any of the processing downstream,” Melliar-Smith said. “And so we, in fact, have been able to do that. They can take the wafers out of the imprint tool and put them in their etch tools and pretty much etch them exactly the same way that they’d etch them if they were using a photoresist-exposed wafer. In fact, one of the things that Toshiba showed were some very nice sidewall profiles using their etch technology after they’d patterned them by e-beam lithography.”
Memory customers, in particular, are pushing to get the highest density they possibly can, Melliar-Smith noted. So the fact that Toshiba has so quickly taken its imprint tool and seen how far it could go with it is not surprising, he said, adding that the 18 and 24 nm features were probably determined by the quality of the imprint masks that Toshiba had access to.
The finest features made by imprint lithography in a lab setting are <5 nm — a dimension that is controlled essentially by the imprint mask. “Without any change in the tooling, except possibly the improved overlay capability and alignment, you could use this technology literally down to a point where the CMOS devices don’t work because of device physics,” Melliar-Smith said. “So this is literally the last lithography that anybody is going to need, at least in CMOS.”
There is considerable industry indecision about what lithography technology will be used beyond the 32 nm half-pitch. Although extreme ultraviolet (EUV) lithography had been considered necessary at that point, it is now unlikely that it will make its entrance by then. Instead, lithographers are likely to rely on a combination of 193 nm immersion lithography and double patterning techniques to get the resolution necessary for critical layers. Beyond that, however, the race is still far from decided.
MII, of course, is making the case for nanoimprint lithography. “Once you get down to 22 nm half-pitch, there’s a lot of certainty that 193 will find it very difficult to do that,” Melliar-Smith said. “They’re talking about using every trick in the book — multiple exposures, very high NA [numerical aperture]. It’s going to be expensive and difficult. And I think people are now really beginning to look for a technology which is at the bottom of the S curve, and is able to provide a much more facile capability, much better lithographic capability, than trying to squeeze the last few percent out of photons.”
Although imprint lithography is indeed a technology at the bottom of the S curve, some concerns have included defectivity and overlay. The Toshiba results could help to allay those concerns.
