Nanowires Hold Promise for Future CMOS

David Lammers, News Editor -- Semiconductor International, 10/8/2007 8:37:00 AM

The semiconductor industry will continue to see performance improvements after CMOS gate scaling runs up against physical limits, said Hiroshi Iwai, a professor at the Tokyo Institute of Technology. Researchers can achieve higher transistor densities by pursuing reduced operating voltages, and nanowire or nanotube-based field-effect transistors (FETs) will eventually play key roles as well, he said.

In a keyote address at the recent Fourth International Symposium on Advanced Gate Stack Technology, Iwai described an interim period coming after the end of CMOS scaling and prior to the introduction of exotic devices based on quantum spin, molecular or other revolutionary forms of logic.

After 2020, Iwai said, CMOS-based devices will continue to be mainstream, with reduced supply voltages serving to increase the number of transistors that could be packed on a single chip. Now, the number of transistors on a chip is limited by power, but researchers have promising approaches to reducing the supply voltage without downsizing the gate length (one example is subthreshold voltage CMOS being pursued by Anantha Chandrakasan at the Massachusetts Institute of Technology [MIT, Cambridge, Mass.]).

Multiple nanowires in multi-gate devices could increase the drive current of future CMOS devices.

FETs based on germanium, III-V materials or carbon nanotubes “would still be a little early for 2020, though they are good candidates afterwards,” said Iwai, a former Toshiba R&D manager.

Instead, devices could achieve high conduction at low voltages by using 1-D ballistic conduction, increasing the number of quantum channels and the number of nanowires or nanotubes in the channel.

FinFET-type structures with four conduction channels made of 1-D nanowires could achieve very high drive currents, he said, estimating that each wire could drive 77.5 mA at a 1 V power supply.

“This is an extremely high value,” he said, noting that already 21.6 mA/wire at 1.2 V was achieved experimentally by the Institute of Microelectronics (IME, Singapore), where the wire diameter equaled 3 nm. “By adjusting the wire width, the energy band mimimums become closer and we can increase the number of the conduction channels,” he said, with four bands likely for silicon-based nanowires.

By taking a vertical device in which the gate wraps around the channel and forming multiple nanowires to form discrete, complementary channels, charge-based devices could be extended much further than some are predicting, Iwai said.

Japan’s central government is launching a nanoelectrics research program in November with eight projects to consider nanowires, germanium-based devices and other programs, said Shinichi Takagi, a professor at the University of Tokyo.

In the United States, the Nanoelectronics Research Initiative (NRI) is part of a wider effort to discover a new logic switch that could be the successor to today’s charge-based CMOS logic. Electrons have been shown to have spin effects and pseudo-spintronic effects that can be manipulated to form a new computational state variable. Many of these experimental devices rely on detection of minute magnetic fields.

A roadmap from Japan's technical community sees silicon nanowires extending the reach of multi-gate devices.

One field of research is quantum-point contacts, and another relies on quantum tunneling through different material layers. Thus far, much of the research is being done at the simulation level, and experimental evidence has been under low-temperature conditions.