Web Exclusive: Inline Detection, Analysis Find Invisible Electrical Defects Faster
In-fab fast electrical testing on specially designed CV short-flow test wafers and automated FIB/SEM defect analysis provides an order-of-magnitude reduction in non-visual defect detection and analysis times, and excellent sensitivity across several design parameters with sufficient sampling to support statistically significant assessments.
Michael Schmidt, Hyoung Kang and Larry Dworkin, FEI Co., Hillsboro, Ore.; Kenneth Harris and Sherry Lee, PDF Solutions, San Jose -- Semiconductor International, 10/1/2007
From a yield perspective, the only defects that truly matter are those that affect product yield. The rest are just a nuisance and any time spent on them is wasted time. Most inline inspection and defect detection methods are focused on visual defects, which may or may not affect performance. Correlation with product yield is generally not possible until electrical test data becomes available after processing is complete. Of course, we have learned to make pretty good guesses about which visual defects are important and which are not based on composition and morphology. However, as devices become smaller and new processes introduce new structures and materials, an increasing fraction of killer defects are non-visual — invisible to conventional inline inspection technologies. They are primarily found only by electrical testing days or weeks after they occur.
To address these shortcomings, a new inline detection methodology has been developed that detects non-visual electrical defects 10× sooner than conventional approaches.1 In addition, it provides electrical data that may be correlated with visual defects to aid in discriminating the killer defects from the nuisance defects. Faster defect detection and root-cause analysis has been shown to shorten process development and yield learning cycles, accelerate the ramp to volume, and speed recovery from yield excursions, bringing new products to market sooner and enhancing yield and profitability in high-volume production.
Visual defect detection methods are fast and can be performed on product wafers at almost any point in the manufacturing process. In comparison, conventional approaches to non-visual defect detection are limited in several ways:
- They typically rely on electrical tests of product wafers or SRAM test structures, followed by intensive visual investigation and off-line failure analysis.
- They can only be applied late in the manufacturing process.
- The defects they detect can be difficult to relocate and analyze on the product wafer or test structure.
- SRAM test structures may not be sufficiently sensitive to capture small defects.
- They require a large number of wafers to provide statistically significant results at the few ppb level required to assure stable yields at 90 nm and beyond.
- Failure analysis in a lab outside the fab can take many days.
The new technique addresses these limitations.2 It combines fast, in-fab electrical testing on specially designed short-flow test wafers with automated focused ion beam (FIB) and scanning electron microscope (SEM) analysis to provide actionable failure analysis results in hours rather than days (Fig. 1).
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| 1. Short-flow test methodology combines in-fab electrical testing of specially designed short-flow test wafers with FIB/SEM analysis to provide actionable failure analysis in hours rather than days or weeks. |
Methodology
Test wafers, known as characterization vehicles (CVs), contain test structures specifically designed to be sensitive to design-process interactions that impact product yields. The CVs contain structures customized for specific processes or process modules. CVs cover most front-end-of-line (FEOL) and back-end-of-line (BEOL) issues, and can provide comprehensive coverage of systematic and random defect mechanisms with statistical sensitivity in the 1-3 ppb failure range using only three to six wafers. Moreover, because the CVs are short-flow test chips designed to be manufactured in days (compared with months in the case of full-flow product wafers), substantially faster learning cycles can be realized.
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| 2. The location of the break in this long chain via structure is easy to see with voltage contrast imaging. The change in surface potential affects the strength of the secondary electron signal from which the image is formed, permitting the operator to quickly find and mark the exact location of selected defects. |
When electrical testing is complete, the wafer and device under test (DUT) location data that contains the defect are transferred to an inline, full-wafer dual-beam FIB/SEM for detailed characterization of selected defects. Dual-beam defect analysis uses the FIB to cut cross-sections through selected defects, revealing subsurface structure for high-resolution imaging with the SEM. The ion and electron beams are configured so that the SEM can image the FIB cross-section after it is milled. The automated high-speed stage quickly and accurately positions defects for cross-sectioning and imaging based on the data received from the electrical tester.
The analysis proceeds in two phases. In the first phase, the operator uses voltage contrast imaging to identify and refine failure locations. Voltage contrast occurs in an SEM image as a result of electrical potential differences at the sample surface. Charge deposited by the scanning electron or ion beam accumulates on non-conductive surfaces or on conductive elements that are not grounded. The accumulated charge alters the surface potential and the strength of the secondary electron signal used to form SEM images. Voltage contrast provides a very fast way to find shorts and opens in microelectronic circuits. Once a defect is located, the dual-beam FIB/SEM automatically mills a fiducial marker with the FIB. In this work, we localized open defects (>100 M-Ω) and shorts (<50 K-Ω) at a maximum rate of about ten sites per hour. Defect sizes ranged down to 50 nm to as large as 40,000 µm2.
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| 3. The defect localized in Figure 2 is shown again here after cross-sectioning. The dual-beam FIB/SEM automatically relocates each marked defect, cuts a cross-section and acquires images. The cross-sectioning and imaging operation takes about seven minutes per site, depending on the number and resolution of the images. |
BEOL module results
The BEOL characterization used a three-layer metal CV test chip from Metal 1 through Metal 3, including vias. The design of the CV included over 1300 product layout variations typical of system-on-a-chip (SoC) products. For example, to characterize the response to via pitch the test chip includes a range of structures with varied pitches and coverage in different top and bottom metal. Another set of structures looks for the influence of metal topography on upper layer metal shorts. The range and distribution of structure parameters are rigorously designed to support statistically significant conclusions in the ppb failure range required for advanced processes while using the minimum number of test wafers.
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| 4. This metal short was located with voltage contrast imaging. The dual-beam FIB/SEM can immediately cross-section the defect. |
The analysis software can also select only defects that were not detected by other inline inspection — non-visual defects. Selected sites can then be exported to the defect analyzer for further characterization. Figure 2 shows a voltage contrast image of one of the defects selected in Figure 1. Figure 3 shows an SEM image of the FIB cross-section of the same defect. A metal void in the lower link of the chain is readily apparent.
The short-flow method can detect shorts as well as opens. Generally, opens are located more quickly (<2 min/site) than shorts (<15 min/site). Figure 4 shows a metal short that was isolated using voltage contrast and FIB techniques.
The poly module CV characterizes shallow trench isolation (STI), polysilicon and silicide modules. It includes a variety of designed experiments with polysilicon structures over both field and active regions, and can provide both functional and parametric characterization. Cross-sectioning and imaging in the dual-beam FIB/SEM can then help to determine the root cause of the defect.
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| 5. This open contact was located with voltage contrast imaging. Foreign residue is the suspected cause. |
The fraction of defects that cannot be detected by conventional inspection techniques has increased with each decreasing technology node. Conventional methods of detecting these non-visual defects cannot be applied until wafer processing is nearly complete. The delay detecting and analyzing these non-visual defects lengthens process development and yield learning cycles, slows ramps to volume production, and puts substantial work-in-progress at risk in high-volume manufacturing.
The technique described, combined with automated FIB/SEM defect analysis, can provide an order-of-magnitude reduction in non-visual defect detection and analysis times. The rigorously designed test structures provide excellent sensitivity across a range of design parameters, with samples sizes sufficient to support statistically significant assessments at the level of a few defects per billion. The technique combines reliable detection of killer defects with excellent discrimination against nuisance defects. All of these benefits contribute significantly to shorter product and process development cycles, faster ramps to profitable volume, and faster recovery from yield excursions.
Acknowledgements
The authors would like to thank Sa Zhao, Stephen Lam, Irfan Saadat and Steve Poon for their help and support.
| Author Information |
| Michael Schmidt received his degrees in applied physics and mathematics at Linfield College. He is currently a senior application development engineer at FEI Co. |
| Hyoung H. Kang received his Ph.D. in materials science and engineering from the University of Maryland at College Park. He was previously an applications engineer with FEI Co., and is now a process limited yield analysis engineer at IBM. |
| Larry Dworkin received his Masters in physics at the University of California-Los Angeles. He is currently a product manager at FEI Co. |
| Kenneth R. Harris received his Ph. D. in chemical engineering at the University of California-Davis. He is currently applications manager at PDF Solutions. |
| Sherry F. Lee received her Ph. D. in electrical engineering from the University of California-Berkeley. She is currently senior director in the marketing and development organization at PDF Solutions. |
| References |
| 1. Michael B. Schmidt et al., “New Methodology for Ultra-Fast Detection and Reduction of Non-Visual Defects at the 90nm Node and Below Using Comprehensive e-Test Structure Infrastructure and Inline DualBeam FIB,” ASMC 2006. |
| 2. D. Ciplickas, S.F. Lee, A. Strojwas, “Critical Features: A New Paradigm for Evaluating IC Yield Loss,” Solid State Technology, 2001. |
