IEDM Focus: Metal Gates/High-k for 45 nm

Intel (Santa Clara, Calif.) and IBM (Yorktown Heights, N.Y.) made news in January when both companies announced that they would be putting metal gate and high-k gate dielectrics into production by the end of the year for the 45 nm device generation. The main reason for doing so? Out of control leakage currents that sap power and generate excessive heat.

Traditional gate dielectrics — primarily silicon dioxide — have to be incredibly thin to maximize capacitive coupling from the gate to the channel to keep drive currents high. They measure only 1.2 nm thick, the equivalent of about four atoms, and have reached the limit — any thinner would result in high leakage current. High-k offers a way to move to a thicker material, which helps reduce leakage while good capacitive coupling remains. Metal gates offer some performance advantages in their own right, but are a required companion for high-k films because of problems at the high-k/silicon interface.

This year's International Electron Devices Meeting (IEDM), to be held Dec. 10–12 in Washington, D.C., will feature two sessions devoted to high-k/metal gates. Advancements are also highlighted in other papers on system-on-a-chip (SoC) and reliability.

At IEDM, researchers from Intel will unveil key details of this 45 nm technology. Highlights include 1 nm electrically thick high-k dielectrics; dual-band edge work function metal gates; trench contact-based local routing; third-generation strained silicon; nine layers of copper interconnects with a low-k interlayer dielectric (ILD); low-cost 193 nm dry patterning for critical layers; and lead-free packaging. Intel has used the process to manufacture a 153 Mb SRAM memory array with an SRAM cell size of 0.346 μm², as well as multiple microprocessors.

A team from UC Berkeley, Intel, Sematech (Austin, Texas), University of Texas at Austin, Advanced Micro Devices (AMD, Sunnyvale, Calif.), IBM and the Molecular Nanoelectronics Lab, GIST (Gwangju, Korea) will report on the impact of flash annealing on performance and reliability of high-k/metal gate MOSFETs for sub-45 nm CMOS. They will show that flash annealing can retain high-k/metal gate stack integrity, while achieving ultrashallow junction (USJ) benefits.

Out of Japan, University of Tokyo and MIRAI (Tsukuba, Japan) researchers are slated to describe how they successfully fabricated a 0.5 nm FUSI NiSi/HfO₂/HfSiO_x/Si gate stack structures with a gate-first process. An HfSiO_x interfacial layer was formed by a cycle-by-cycle deposition and annealing process, followed by in situ layer-by-layer deposition and annealing for HfO₂ growth. The end result was a gate leakage current of ~4 A/cm² at V_fb + 1.0 V and an effective electron mobility of 120 cm²/V_sec at 0.8 MV/cm.

NEC (Tokyo) will describe a metal gate fabrication process suitable for extremely small, low-voltage SRAM cells at the 45 nm node, and possibly for embedded DRAM applications as well. One way to produce a metal gate is to diffuse a metal through an existing silicon gate. The resulting material, a silicide, is considered to be metal. However, it is difficult to control the specific electrical phase, or the precise electrical characteristics, of the silicide formed by this metal-silicon reaction. The NEC team will describe how they did so by tightly controlling formation of a critical boundary between complementary n- and p-type gate electrodes. Their process yielded low gate resistance and low-voltage operation, which they demonstrated with an 0.446 μm² SRAM cell that operates at 0.8 V.

MIRAI-Selete’s concept of single-metal, dual-gate complementary MISFET features a single TiN gate on a MgO- and Al2O3-containing HfO2-based high-k layer. The band diagram is shown on the right.

Metals with specifically tuned work functions are desirable for n- and p-type devices. A challenge here is that metal is hard to etch, therefore it is difficult to control the profile of a metal gate, including such aspects as taper, critical dimensions (CDs) and linewidth roughness (LWR). All of these metal gate-related issues lead to difficulty in controlling threshold voltage (V_t), which is essential to proper operation of the devices. MIRAI-Selete researchers sidestepped these issues in aggressively scaled complementary MISFETs (Figure) by employing one common TiN metal gate but using different high-k insulating layers for the n- and p-type devices. They used HfMgO for the n-type, which enhanced electron mobilities and reduced charge trapping (PBTI). They used HfAlO for the p-type, which lowered V_t.

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