WLP vs. 3-D Integration: Where's the Line?

Where do you draw the line of distinction between wafer-level packaging (WLP) and 3-D integration? Ask a handful of people, and you're likely to get some very different answers.

"In terms of general WLP trends, through-silicon vias (TSVs) are getting a lot of attention right now," said Dan Schmauch, WLP product manager at Semitool (Kalispell, Mont.). "But is TSV really a packaging application, or is it the next generation of interconnect? We're noticing some crossover and increasing gray boundaries between the two."

The blurring in distinction between WLP and 3-D integration is not going unnoticed by the industry, but there are distinct differences in the two. "Wafer-level packaging occurs when the packaging step is done at the wafer level," explained Belgacem Haba, Tessera Inc.'s (San Jose) CTO of Packaging and Interconnect. "3-D packaging is the vertical stacking and interconnection of multiple similar or dissimilar devices that have been either previously packaged or are in bare die form. We are seeing some blurring in the emergence of 3-D WLP technologies, where wafers are stacked on top of each other, connected using through-silicon vias or other technologies, then diced. The end result is a vertically stacked, 3-D package — the packaging step is performed at the wafer level. Yield issues that emerge from this approach can be addressed by reconstituting wafers with only known good die."

And Jan Vardaman, president of TechSearch International (Austin, Texas), weighed in on the issue of blurring: "There's some confusion with people calling 3-D TSVs a wafer-level package, because it's a technology," she said. "I'm trying to differentiate it a little bit, because it's not a package. It goes into the package, but it's not the package. It's an interface."

What other WLP trends are companies noticing? "Redistribution is beginning to pick up," noted Paul Siblerud, Semitool's vice president of WLP/electroplating. "And there are some new nuances with copper pillars that are being commercialized fairly aggressively now. We saw TSVs emerging as a trend about a year ago, and now that's starting to really take off, although it's still in the early stages. That's a trend we'll be seeing more of, especially once all of the design tools are there and chipmakers can really take advantage of the TSV technology."

Tighter collaboration between companies is yet another trend Siblerud has spotted. "It's interesting, especially in advanced packaging applications, how they've become a collaborative affair," he said. "If you drew a map of all the companies doing wafer-level style packaging and connected the lines of who's doing business with whom, it's a mess of a picture because there are so many designs and devices being transferred all around. In the past, companies kept things to themselves and called advanced packaging a 'value-add' feature. Now we're seeing the interaction between the design of the device and the package. That's more than foundry packaging houses can handle, so they're pursuing relationships with the front end. We're going to see some interesting times in the years ahead."

The various process steps involved in creating one of Tessera’s wafer-level chip-scale packages (WLCSP, wafer encapsulation [a]; electrical contacts are routed [b]; solder bumps are formed [c]; and the wafer is singulated [d]). The final wafer is one chip short of a WLCSP (e). (Source: Tessera Inc.)

How about market trends? The WLP market is continuing its strong growth, driven especially by high-end mobile phones. An interesting development is that WLP is turning up in unexpected applications — even in low-end mobile phones. Which is somewhat of a surprise, given that WLP is a relatively expensive technology.

"We recently took apart two low-end Nokia phones made in India," Vardaman said. "They have wafer-level packaging inside. As far as trends go, we're seeing larger die sizes, ball size increases, and we've found lots of these in teardowns that our partner, Total Process Solutions Study Group, does in Japan. Another trend is that people are extending the technology with the use of the embedded WLP concept."

And a challenge associated with WLP and larger die sizes is that it makes reliability questions come up more, according to Vardaman. "Then there's the question of whether you need to underfill or not for the larger sizes. That's an open question as the die sizes get larger," she added.

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