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Managing Heat Flux in Advanced Packages

Wafer-level heat transfer, thermal interface materials, underfills and heat spreaders all contribute to thermal management.

Andrew Delano and Devesh Mathur, Honeywell Electronic Materials, Spokane, Wash. -- Semiconductor International, 10/1/2007

Today's computers come equipped with nearly a billion transistors handling billions of calculations every second. However, packing all this computer power into an area the size of a coin creates a significant thermal challenge in the chip. In fact, the average desktop computer could very well have localized hot spots that dissipate more heat per unit area than the throat of a rocket nozzle or a space shuttle during reentry into the Earth's atmosphere (Fig. 1). This article explores how microprocessor packaging engineers keep the chips cool without shortened chip lifetimes or failures. It also provides a look at the issues and options facing the industry and the advanced materials designed specifically to meet this challenge.

Semiconductor manufacturers rely on the chip packaging process to address three main areas. The first is connectivity — providing I/O functionality. The second relates to the need to protect the chip and insulate it from potential damage. Finally, the third area pertains to thermal management, which is the need to dissipate heat generated by high-powered chips. Much of this article focuses on packaging for heat dissipation, as it is a critical emerging need. Also, for the sake of simplicity and illustration, we focus on a flip-chip architecture, which is a type of package that does not require wire bonds — instead, the final wafer processing step deposits solder bumps on the chip pads, providing the connection to the external circuitry (Fig. 2). In this design, heat is drawn primarily from the backside of the silicon because the circuitry is on the front. We focus on this package type simply because flip-chips are used in the most demanding applications where issues of addressing heat flux are critical. These concepts, however, are applicable in other packaging approaches as well.

The primary thermal management objective of the modern microprocessor package is to reduce the heat flux to a more manageable level while keeping the temperature of the processor below ~100°C. Presently, this transformation takes place with the use of three types of advanced materials known as "thermal interface material 1 (TIM1)," the "heat spreader" and "thermal interface material 2 (TIM2, Fig. 3)." TIM1 facilitates heat transfer from the silicon backside of the chip to the heat spreader (or heat pipes in some cases), where the high-heat flux is lowered. TIM2 then facilitates heat transfer to the next component (a heat sink, for example). Together, these materials account for ~40% of the total thermal budget (Fig. 4). Optimum design, therefore, coupled with a good choice of materials and interfaces, makes a big difference. Before we look at the details of these materials, we will explore the heat flux in the wafer itself and identify approaches being taken to optimize that area.

1. This image demonstrates the heat flux challenge, comparing hot spots on today’s microprocessors with rocket nozzle throats and the space shuttle’s reentry.

Heat flux across the wafer

The heat generated by a microprocessor must first be conducted through the silicon. While silicon itself is a reasonably good thermal conductor, reducing the distance that the heat must travel provides additional benefits. For this reason, silicon wafer thinning is gaining attention. Historically, this approach has allowed manufacturers to reduce the silicon wafer thickness from ~800 to 150 μm, depending on wafer size and package type. One of the easiest ways to thin wafers is by mechanical grinding or chemical mechanical polishing (CMP). While these approaches are easy, they are limited in terms of how thin they can make the wafers because of damage to the wafer that is inherent in both processes. Some recently introduced leading-edge technologies can thin wafers beyond 50 μm. Such technologies have implications for high-heat flux applications, as well as chip-on-chip, package-on-package (PoP), low-stress applications, or a combination of these.

2. Flip-chip architecture is a type of package that uses the final wafer processing step—rather than wire bonds—to deposit bumps on chip pads to provide connection to external circuitry.

3. Current microprocessors use a combination of thermal interface materials and a heat spreader.
Furthermore, bulk silicon etchants are available that can remove up to 30 μm/min to achieve the final wafer thickness. This is then followed by surface finishing options, depending on desired properties. A silicon polish etchant can be used for a smooth finish, removing 5 μm/min. For a rougher finish, a silicon texture etchant, which also removes ~5 μm/min, can be used. The choice is based on thermal requirements, interface, adhesion and backside metallization properties. Final roughness affects solder-based thermal interface materials that are applied to the backside of the die.

TIM1

The highest heat flux in a computer occurs in the microprocessor, so providing a high-performing thermal connection at this interface is critical. To accomplish this, an engineered material — TIM1 — is used. Without it, two supposedly flat, smooth surfaces (i.e., the silicon and heat spreader) only make physical contact in as little as 5% of the total contact area (Fig. 5). In the past, this material was typically metal powder-filled silicone grease. With increasing heat flux, metal solders have replaced grease to reduce resistance to heat flow.

While metal solders provide superior thermal performance, they do have drawbacks. First, to bond to the processor, the backside of the silicon must be metallized, which adds cost. Second, metallic TIMs are relatively rigid, and this may cause stress if the silicon has a different coefficient of thermal expansion (CTE) than the heat spreader, which is usually the case. Finally, the solder itself is expensive.

An optimum solution combines the stress-free properties of grease with the thermal performance properties of solder. By incorporating solder powder in a polymer matrix, it is possible to realize good solder thermal performance, along with low stress and low cost. In these TIM1 materials, referred to as "advanced polymer solders," the solder powder reflows during the cure process to form high-thermal-conductivity pathways between the silicon and heat spreader. Meanwhile, the polymer also cures between the vias to form a flexible matrix. As a result, these materials provide the same thermal performance as solder at lower cost with less residual stress.

4. Thermal budget accounts for each material or device through which heat is transferred.

Heat spreaders

5. Microscopic surface characteristics of the material create a thin but significant gap.
The goal of the heat spreader is only partially described in its name. By spreading the heat, a high-heat flux is reduced and the job of downstream components is made easier. The heat spreader also provides mechanical protection to the delicate silicon. How does a heat spreader spread heat? Ideally, a material with very high thermal conductivity would do the job. However, economic factors usually result in a nickel-plated copper heat spreader. Copper has adequate thermal conductivity, but future processors demand better.

Diamond provides the highest thermal conductivity known to man, although its cost is usually prohibitive. Diamond-metal composites provide some promise for both increasing thermal conductivity and improving CTE match at an affordable cost. Active cooling techniques may also be used to spread heat. Thermoelectric materials can actually refrigerate hot spots. Finally, liquids may be pumped in circuit or even evaporated or condensed. It has yet to be determined which of these options have a real future.

TIM2

Once spread, the heat must then be transferred to a device that carries it to the environment. Transferring the heat to such a device is the work of the TIM2. Similar to TIM1, TIM2 is typically a metal-powder-filled grease, although metal-powder-filled waxes and polymer materials also exist. These materials, called "phase change materials (PCM)," are specifically formulated so that they change phase from solid to liquid just below the operating temperature of the processor. This property makes them easy to handle and helps keep them in place during operation.

The decision to use a grease or PCM involves considerations such as ease of application, reworkability, cost and shelf life. The most significant, however, is reliability. A computer heats up and cools down whenever its power is cycled, and this temperature change affects all of the materials within the computer, causing expansion and contraction. This temperature cycling is especially detrimental for grease-based TIMs because of their low viscosity.

Thermal performance of typical PCM and grease measured against repeated temperature cycling is illustrated in Figure 6. Although both materials perform well from 0 to 500 cycles, the performance of the grease declines and suffers a temperature increase of nearly 2°C by 1000 cycles. On the other hand, the high viscosity of the PCM enables reliable performance for thousands of cycles.

6. Thermal cycling reliability testing is used for product qualification.

A screen-printable PCM was recently introduced to the industry that combines the application flexibility of grease with the superior performance of a traditional pad-format PCM. Although greases have historically been used for TIM2 applications, the advent of screen-printable PCMs has resulted in the industry moving in this direction as the preferred choice.

Conclusion

Careful design and material selection are critical to successful chip packaging for heat dissipation. Accounting for heat dissipation and thermal management from the initial design to final product application will produce more reliable and better performing microprocessors and end products. Further, increasing future thermal management needs can only be met by strong cross-functional and cross-discipline collaboration.


Author Information
Andrew Delano is Honeywell Electronic Materials' R&D manager for interconnect packaging solutions, responsible for thermal interface materials and advanced thermal solutions R&D. He received his Ph.D. from the Georgia Institute of Technology in 1998, and has more than 12 issued patents.
Devesh Mathur is Honeywell Electronic Materials' director of global technology for interconnect packaging solutions, responsible for new products for thermal cooling solutions for IC and related packages. He earned his Ph.D. from Rensselaer Polytechnic Institute, and is an expert in the area of thermal management, six sigma, polymers, and process scale-up and design.

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