Ultralow-k Technology Moves Forward

The development of low-k materials started with silicon dioxide that had a dielectric constant (k) of 4, then to fluorinated oxides, the addition of carbon, and now porosity (Fig. 1). And the advances have been impressive. Today, 65 nm devices with a k value of 2.9 and as many as 11 copper layers are in production (Fig. 2). For the 45 nm node, a k value of ~2.5 is targeted. Arriving at this point has required new chemistries, optimization of the dielectric stack and integration schemes that address maintaining the effective k value and minimizing failure mechanisms.

1. Plasma-enhanced chemical vapor deposition (PECVD) has successfully deposited ultralow-k films containing nanopores and exhibiting robust mechanical integrity. (Source: Applied Materials)

Low-k material

"The most important recent advances in ultralow-k dielectrics is the significant progress in plasma-enhanced chemical vapor deposition in lowering the k value," stated Rudy Cartuyvels, director of interconnect, packaging and system integration at IMEC (Leuven, Belgium).

Just five years ago, spin-on materials were among the first to lower the k to the 2.0 range, while plasma-enhanced chemical vapor deposition (PECVD) was lagging a bit behind. However, poor mechanical properties, such as a low Young's modulus and pore sizes in the range of 3–10 nm, made them difficult to integrate. Poor adhesion made surviving the chemical mechanical planarization (CMP) process unlikely, and the large pore sizes created barrier integrity problems, such as pinholes, that compromised the reliability of the interconnects. A high coefficient of thermal expansion further threatened the entire interconnect structure during reliability experiments involving thermal cycling.

Since then, PECVD has made significant progress in lowering the k value to 2.5, with a Young's modulus of 10 GPa. Some Japanese companies make hybrid stacks mixing very porous spin-on dielectrics with a more dense PECVD or spin-on material. Still, the bulk of low-k materials are deposited with PECVD.

2. TEM of a cross-section of a 65 nm CPU using low-k technology (2.9) shows 11 metal layers. Comparable devices are in development for the 45 nm technology node. (Source: Texas Instruments)

To maintain a low k value, the remaining matrix material must contain chemical bonds with essentially no polarity because such bonds generate higher k values. Given that polar bonds can occur after the integration process, the film must remain hydrophobic, repelling moisture and water, which are polar species.

"We are now at the stage of lowering the k value down to the 2.2 k range, with 2.5 having reached a maturity level and ready to go to manufacturing at the 45 nm node," Cartuyvels asserted. However, questions of mechanical integrity grow as porosity levels exceed 30% (Fig. 3).

3. Young's Modulus and pore diameter as a function of porosity for low-k dielectrics has evolved to the development of low-k materials with higher Young’s moduli (left) and reduced pore size (right). (Source: IMEC)

Process integration

Integrating ultralow-k (ULK) materials into the manufacturing process has been an industry effort. Having developed ULK films with robust mechanical integrity, equipment manufacturers like Applied Materials (Santa Clara, Calif.) turned to process solutions to ensure the films would withstand etching, ashing and CMP.

The addition of carbon to the dielectric material introduced a myriad of problems, including film cracking and adhesion issues. Through unique interface engineering, Applied Materials was able to strengthen the adhesion between the nanoporous low-k material and the underlying barrier film by depositing an oxide adhesion layer. The result is a smooth, interface-free transition from the adhesion layer to the bulk low-k film, allowing it to withstand the horizontal shearing action of the CMP process, claimed Derek Witty, managing director of Applied Material's Blanket Films Group.

Germane to the fabrication process are aggressive chemistries required to etch through oxides, ash carbon-based photoresists and polish metal layers. Unfortunately, these very aggressive chemistries attack the low-k material lining the sidewalls of trenches and vias, effectively removing carbon and increasing the k value. While process integration steps will typically increase the k value by 0.1, the loss of carbon can increase k several times more.

In the past, O₂N₂ ash chemistries were commonly used with the oxygen acting as an oxidizing chemistry. Today, more reducing, softer ashing chemistries are being used. A move to softer chemistries for pre-cleans prior to physical vapor deposition (PVD) metallization are also being introduced, as is the use of organic solvents for wet cleans. The interest in ensuring manufacturability is extended to CMP equipment suppliers who are working to decrease the downward force during polishing while maintaining effectiveness.

Damage control

Higher porosity of dielectric films increases the chance that solvents, precursors, plasma species and metal barrier materials will diffuse into the pores. To avert a rise in dielectric constant, higher leakage currents, and poor device reliability, pore sealing techniques^1-3 have been developed to prevent and/or repair damage occurring during process integration.

One approach, a plasma treatment called sidewall densification, is designed to prevent metal precursor penetration into the ULK material. Pore sealing is particularly important when the metal barriers are deposited by atomic layer deposition (ALD) because of the extent of penetration into the ULK. Studies, for example, indicate a significant reduction in ALD precursor penetration into blanket nanoclustering silica (NCS; k~2.2) films that have undergone sidewall densification. In comparison, an untreated as-deposited NCS film exposed to the same ALD deposition process was shown to contain a high concentration of the precursor throughout the depth of the film.

Primary to the densification approach is control over the thickness of the densified layer at the feature/trench sidewalls. Because the densified layer has a higher k value than the underlying film, it must therefore be just thick enough to achieve pore sealing. This critical step can be accomplished by tuning during an in situ plasma treatment (Fig. 4), noted Peter Loewenhardt, managing director of etch products at Lam Research (Fremont, Calif.).

4. Shown in 500× S/TEM images of Metal 1 nanoclustering silica patterned features with various densified sidewall layer thicknesses that were tuned during exposure to in situ plasma densification treatments. (Source: Lam Research)

A second pore sealing approach, sidewall film deposition, fills the pores on the sidewalls of patterned features with a thin, conformal protective film, which itself has a low k value. A relatively new technique, etched and stripped trenches with conformal deposition were measured with ellipsometric porosimetry following treatment, and no toluene or water adsorption was indicated in the film.

Finally, silylation approaches can potentially be used to simultaneously seal ULK pores and repair plasma-induced damage.⁴ Silylating agents bond to silanols and contain organic groups that replenish the depleted carbon, thus restoring the k value of the ULK. If designed properly, the silylating agents may also seal the pores. While this technique shows promise, it requires an additional chamber and processing step.

Optimizing stack films

Despite the effectiveness of increasing the amount of porosity in the ULK film, beyond 30% or a k value of 2.5, manufacturability is likely to decline. However, "it is possible that 2.5 will be good enough for the 32 nm node if you can scale some of the other materials in the dielectric stack," said Greg Shinn, director of advanced CMOS interconnect technology at Texas Instruments (Dallas, Texas).

The dielectric stack contains multiple layers, including the bulk low-k dielectric and etch-stop and cap layers. These support layers typically have higher k values and degrade the effective dielectric constant of the stack. By optimizing thickness and reducing the dielectric constant of the layers, Texas Instruments has demonstrated feasibility and a lowering of the effective k value.

For the 45 nm node, a silicon carbonitride (SiCN) film with a k value of ~5 can serve as an etch stop, as well as a metal barrier, atop the copper film to prevent metal migration across the interface. In the formation of the SiCN films, ammonia-type precursors are used. If etching into the film occurs, ammonia can diffuse up to the top of the stack and poison the photoresist used to pattern the ULK. Therefore, a second etch stop consisting of a dielectric, such as an oxide or another variant of silicon carbide or silicon carbon oxide, is sometimes placed on top of the first. It is possible, however, to eliminate the top film by using new patterning stack technologies that essentially put the oxide film within the patterning layers.

Continued work on SiCN films for next-generation dielectrics and adequate electromigration performance will be of particular importance for 32 nm technology, Shinn noted.

Air gap technologies

Current low-k dielectrics can be extended to 2.0 using known solutions. To reduce the dielectric constant further requires increasing porosity beyond 50% to 70% or 80%, theoretically dropping the k value to about 1.5 and, in the process, becoming an integration nightmare. However, if the dielectric between the metal lines is completely removed, then the k value is theoretically one. This is the basis of air gap technology, "the ultimate way of scaling the k value," Cartuyvels said.

There are several approaches to creating air gaps in the device structure. In general, traditional interconnect process schemes are followed with lithography steps added to define and remove the dielectric.

The approach developed at IMEC essentially creates air gaps throughout the device structure. A thermally decomposable material (TDM) is deposited between the metal lines in the region where the interconnect structure will be built. On top of the TDM, a porous hard mask is deposited, followed by the remaining metallization process. This is a classical damascene process, with the low-k dielectric being replaced with a TDM. A combination of heat and a UV cure follows, completely disintegrating the TDM, which evaporates through the porous hard masks. An effective k value was measured between 1.5 and 2.0 depending on the k value of the porous hard masks, which remain in the structure.

"The challenge with air gap devices will likely be reliability in terms of packaging because of the serious impact on the mechanical integrity of the interconnect," Cartuyvels said. Therefore, while promising an alternative to increased porosity, air gaps will still need to prove structurally sound to become production worthy.

Economic concerns

Technical advances and feasibility in ULK is likely to continue through the 32 nm node (Fig. 5), although not necessarily in keeping with the International Technology Roadmap for Semiconductors (ITRS). Timing not withstanding, the showstopper is likely to be the cost of continued scaling, noted Sitaram Arkalgud, 3-D interconnect director at Sematech (Austin, Texas). Therefore, Sematech, among others, are looking ahead, weighing performance and cost benefits in search of future options. With a bead on productivity, 3-D through-silicon interconnects appear to be a viable contender to pick up beyond scaling, not 3-D packaging or assembly technology, but stacks connecting, for example, logic, analog and leading-edge memory (DRAM) and flash, each on different levels. And rather than transmitting signals in and out of each I/O at each level, which does not provide much performance benefit or power reduction, I/Os would ideally reside on one level only. Everything else runs internally, all stacked up on top of the other. Breaking up the different levels and running them at an appropriate technology node provides good economic sense, according to Arkalgud. How this all plays out in the next few years is anybody's guess. This is just one of many scenarios yet to surface.

5. The dielectric constant continues to steadily decrease, but not at the targeted pace of the International Technology Roadmap for Semiconductors (ITRS). (Source: Sematech)