Copper Barriers Hold Up Under Stress

The technology behind the traditional tantalum-based barrier and copper seed is being successfully applied to future generations using various ionized physical vapor deposition (PVD) schemes. How far PVD technology can be extended is unknown, although it seems clear that it will satisfy the requirements of the 32 nm generation. "The issue is real estate management. How do you make the deposited films thin enough and conformal enough, while leaving an opening at the end for the electroplating? At the 22 nm node, even with only 1–2 nm of barrier on each side, with the copper seed overhang, the technology will have to be improved to fill a 40 nm trench," said Makarem Hussein, senior principal engineer of components research at Intel Corp. (Hillsboro, Ore.).

1. Barrier and seed conformality in covering ~64-nm-wide trench in a gap fill test structure. The copper seed (deposited by PVD) is continuous with an overhang that occupies ~28 nm of the trench CD. The opening is acceptable for good trench fill, but there is risk of copper seed pinch-off and seed discontinuity for smaller features. (Source: M. Hussein, Intel)

2. A 100 nm via with a 12:1 aspect ratio achieves ~100% step coverage by ionized ALD TaN barrier. (Source: Novellus)

PVD limits?

The copper barrier technology, widely adopted on multi-level interconnects in logic devices and just recently applied to DRAMs, uses a sputtered TaN barrier, a tantalum glue layer, a PVD copper seed layer and electroplated copper fill. The seed layer must be continuous to carry current. Good copper wetting (uniform coverage without agglomeration) also contributes to EM resistance.

Up until around the 65 nm generation, with Metal 1 (M1) trenches around 80 nm wide (Table 1), this technology worked quite well. In making the critical transition to the 45 nm node and M1 trenches of ~60 nm, the barrier and copper seed have scaled through the use of various ionized PVD processes.

In ionized PVD, step coverage is enhanced by a resputtering mechanism. DC power and substrate AC bias are optimized for step coverage. "In a single PVD step, the tool deposits a non-uniform step coverage, which is simultaneously resputtered by argon or the metal ions, allowing a redistribution of the material on the sidewalls to solve the step coverage problem," Edelstein explained. "At the same time, a reasonably thick material is deposited on the top surface without pinching off, which is good for electroplating and copper grain growth."

Beyond the pure physics of filling narrow trenches, the effect of the barrier on overall line resistivity is also key to RC delay. As far as the barrier (TaN) is concerned, PVD is delivering ALD-like thicknesses in the 3-4 nm range. This is important because extendibility is threatened not only by shrinking dimensions, but also by net resistivity concerns and overall RC delay. "PVD's unique capability to deposit high-purity materials cannot be matched by other alternatives like ALD," said Prabu Gopalraja, vice president of the PVD division at Applied Materials (Santa Clara, Calif.). "The challenge we have seen with ALD solutions is that they are substrate-dependent and that nucleation characteristics will be different on different substrates," he added. "In addition, you can't choose all the materials you need by ALD; for example, pure tantalum," Edelstein said.

The ruthenium option

One of the most viable alternatives to the tried-and-true TaN/Ta/Cu stack¹ involves ruthenium (Ru). Not only can copper be directly plated on ruthenium, eliminating the copper seed overhang problem, but it also has a low bulk resistivity (7.6 μΩ-cm vs. 13 μΩ-cm for tantalum). Unfortunately, ruthenium does not provide a very good barrier to copper, oxygen or water, so a TaN layer, or some other barrier, is still needed. "The move to ruthenium is driven by the need for reduced thickness from a line resistance standpoint, so you can go to ionized ALD TaN and then deposit the ruthenium also by ionized ALD as an adhesion promoter, so the ruthenium is really playing the role of tantalum in the TaN/Ta stack. This has advantages for very high aspect-ratio features," Smith said.

Unfortunately, if ruthenium has to wait for ALD to be implemented, it may be waiting for some time. ALD is still hindered by low throughputs and high cost relative to PVD. Fortunately, ruthenium can be deposited by chemical vapor deposition (CVD) as well. "CVD is a more practical alternative because of contamination and run-rate concerns of an ALD system," Hussein said.

Perhaps an even simpler solution may involve sputtering of both the TaN and ruthenium layers, followed by a direct-plated copper process. Using the same conditions as a conventional plating on a seed-Cu/Ta/TaN process, Makoto Ueki and colleagues at NEC's System Devices Research Lab (Kanagawa, Japan) recently showed that 200-nm-wide direct-plated copper lines with highly (002)-oriented Ru/TaN liner have a resistivity that is 12.4% lower than that of the conventional plated copper on TaN.² The lower resistivity was caused not only by the lower bulk resistivity of ruthenium, but also smaller interface scattering. By encouraging Ru(002) growth (at low-pressure and high-power PVD), Cu(111) orientation with larger grains results. The lattice mismatch between Cu(111) and Ru(002) is also small (~6%) relative to that between Cu(111) and Ta(110) (~4× larger), which minimizes interface scattering between the copper and liner. In this study,² there was no significant interface layer between the ruthenium and direct-plated copper, and the bottom and side coverage of ruthenium and tantalum were both ~4 nm (Fig. 3).

3. Comparison of traditional 200 nm wide copper line with tantalum liner (left) and ruthenium liner (right). There is no significant interface layer between the sputtered ruthenium and direct-plated copper. (Source: M. Ueki, NEC)

One of the key challenges associated with going to a ruthenium glue layer is the need to optimize the copper plating process for optimal grain orientation and large grain growth (formerly dictated by the copper seed). Another alternative is to perform a flash copper deposition (~10 nm) prior to plating. In addition, production-worthy chemical mechanical planarization (CMP) processes for ruthenium have to be developed, which is more difficult for a noble metal.

At the same time, this next-generation barrier, whether it is TaN/Ru or something else, will be implemented in conjunction with ultralow-k dielectrics (k<2.5). Compatibility with these porous dielectrics (which may require pore sealing⁴) must be considered. "In general, for reliable integration, you want no damaged material left behind. The main reason is the damaged material is hygroscopic, so if you have a water reservoir next to your metal, you could promote oxidation or corrosion," Edelstein said. He points to intense efforts to improve the low-k (SiOCH) material itself, achieving films with less porosity and less interconnectivity of pores for a given dielectric constant, which results in less susceptibility to plasma damage from etching and stripping processes.

PVD suppliers are offering various forms of remote plasma pre-cleans (rather than active sputtering) to limit low-k film damage. "Using remote plasma hydrogen radical cleans, the integrity of the low-k dielectric can be maintained while the underlying copper oxide is reduced," Gopalraja said.

Ensuring reliability

One of the ways companies improve the reliability of the interconnect is by using a barrier-first approach: performing the punch-through and anchoring of the vias in the lines below prior to barrier metal deposition. This allows improved EM and stress migration (SM) resistance.

As the maximum current density forced through the interconnect (J_max) continues to increase (Table 1), reliability margin shrinks. EM lifetime can be increased by up to 10–50× by adding a selective CoWP capping layer onto the copper lines under the SiN_x or SiC_xN_yH_z cap.⁵ However, this approach, which has been investigated for at least a few device generations, continues to prove unnecessary. "Capping copper with cobalt will make the interconnect immortal to electromigration. So the benefit has been established. But that in itself is not enough to adopt cobalt into manufacturing. Two other factors must be present: The need has to be there, mandated by the maximum allowed current density that my microprocessor design can allow. The other is the maturity of the cobalt electroless plating process. There are a lot of questions around deposition uniformity, defectivity, compatibility with barriers and other issues, and we always find a way to not use it," Hussein said. Edelstein added, "There are two challenges: you need perfect selectivity, and then there are leakage and TDDB mechanisms due to drifting or diffusion of cobalt or other metals. In addition, the nitride or carbonitride cap layer is still needed, so the net effect is the addition of an expensive process step. And, because the nitride layer is needed as an etch stop and as a barrier in the case of unlanded vias, it is unlikely that it can ever be eliminated from this scheme." Finally, cobalt must also be compatible with the ultralow-k dielectric and the barrier. "If you have a porous dielectric and you're trying to do electroless plating of cobalt, cobalt could deposit and migrate through the pores and create leakage," Hussein said.

Nevertheless, selective metal capping layers remain a "back-up" technology solution.

The more likely solution to be used in the meantime includes CuSiN deposition with successively thinner and lower-k dielectric caps. The industry has gradually made the transition from SiN (k~7.0) to SiCN (k~4.9). Some companies are evaluating CuSiN processes to improve the reliability with the barrier.⁶ The process involves three steps: a reducing plasma (H₂/N₂) to convert copper oxide to elemental copper; silane exposure to diffuse silicon into the copper; and a nitrogen-containing plasma (NH₃) to scavenge excess silicon and generate Si-N bonds. Then the SiCN layer is deposited. Smith noted that throughout interconnect processing, reliability is paramount. "The goal is to minimize the native vacancy content in copper films, which leads to voids. By continually optimizing the barrier materials, the tantalum deposition, alloy seed deposition and plating, we're doing a lot of work to reduce the vacancy content without having to introduce an additional film like cobalt," he said.

Barrier alternatives

There are alternative barrier materials as well — most notably, TiN/Ti and manganese. A number of companies that are using nanoclustered silica (NCS, k~2.25) ultralow-k dielectric found the material to be incompatible with tantalum and began using TiN/Ti stacks as a copper barrier. "The main concerns are high resistivity of Cu-Ti alloy and compatibility to the particular CMP process used by the customer. Also, when integrating with porous low-k dielectrics, the dielectrics have a tendency to absorb moisture and, during the barrier/seed deposition process, can oxidize the barrier material, leading to poor adhesion between the barrier and seed and early stress-induced voiding and electromigration failures," Gopalraja explained. He said this problem gets more severe when isolated vias are surrounded by a large volume of dielectric and, hence, have a greater tendency for oxidation.

Still, there are advantages to titanium processes, a primary one being cost. "There is a real cost advantage for titanium, so it might make sense for memory manufacturers. Some customers are in the process of evaluating it in terms of reliability," Smith said.

Manganese (Mn) has been investigated for years as a self-forming barrier. The barrier and seed are formed in a single deposition step, with the manganese migrating to the feature edge during annealing. "The challenge is how to prevent the manganese from diffusing into the bulk of the copper interconnect in order to maintain low copper resistivity, and multiple anneal steps have been proposed," Gopalraja said. He noted, however, that this approach is largely unproven on very small features (<40 nm), and the interaction with porous low-k dielectrics needs to be determined.

Nevertheless, work continues. In a paper to be presented at the upcoming International Electron Devices Manufacturing (IEDM), Hiroshi Kudo and fellow researchers from Fujitsu Laboratories (Tokyo) will show that self-formed MnO over MnO/Ta barrier increases EM by over 45×, reduced resistance of the wiring by 13% and showed no SM failures with 45 nm design rule test structures.⁷ In this study, a full NCS interlevel dielectric (ILD) was used.

Next steps

PVD tool suppliers are continuing to improve their ionized plasma sources to improve the physical properties of the tantalum and copper films, enabling thinner barriers and seeds and larger openings for copper fill by plating. Nevertheless, the point should eventually be reached when these processes can no longer deliver the required solutions, perhaps as soon as the 22 nm node. Ruthenium-based solutions seem to be the most promising because of the possibility of direct plating, low resistivity and excellent lattice matching with copper. But much work is going into self-formed manganese barriers, as well as titanium barriers. Barrier choice will be largely dictated by ultralow-k dielectric choice and integration scheme. Cobalt or other selective metal caps are on hold for now, as reliable interconnects continue to be produced without this added step.