Guiding Chamber Cleaning by FDC, APC
The dielectric chemical vapor deposition (DCVD) process requires periodic cleaning of the chamber walls to prevent flaking of the film that grows on the walls during deposition.
Francesco La Spada and Rosaria Politi, STMicroelectronics, Geneva, Switzerland -- Semiconductor International, 10/1/2007
The dielectric chemical vapor deposition (DCVD) process requires periodic cleaning of the chamber walls to prevent flaking of the film that grows on the walls during deposition. This chamber cleaning is accomplished using either radio-frequency (RF) plasma or remote plasma source (RPS) and fluorinated reactive gases. Because the chamber walls are typically made of aluminum, it is critical to stop the cleaning process before the reactive gases etch the chamber surface and process kit.
A non-optimized clean time on a CVD chamber generates elevated defect density on wafers processed just after the clean. An overclean produces aluminum fluoride (AlF) particles, whereas an underclean results in nitride or oxide flakes on the wafers.
It is common practice to stop the chamber clean based on either a fixed time calculated from the deposited film thickness and an expected film etch rate during the plasma clean; or using an endpoint detector (optical and/or Fourier transform infrared [FTIR]). In DCVD, because all of the relevant process factors (i.e., tool type, film, analysis methods) are typically not held constant, it is not straightforward to establish a relationship among all process factors for advanced process control (APC) purposes.
Clean time by etch rate
Typically, methods used to measure the film thickness accumulated at the tool surfaces gives an inaccurate approximation because of the non-uniformity of the film deposited. Also, the etch rate used in the calculation is not verified very often, and may drift with time. These inaccuracies in etch rate and film thickness cause both underclean — leaving polymers on the chamber walls because of insufficient etch time, while if the etch time too long, the plasma will attack and etch the chamber walls.
Clean time by endpoint
As an alternative, optical endpoint detection is widely used in RF plasma chamber cleaning, providing good feedback for the actual clean time based on fluorine ion saturation in the chamber. When the cleaning condition is achieved, the signal is translated as an input to stop the chamber cleaning time. The disadvantages to this approach are based on the reliability of the detection mechanism for determining the cleaning condition, and the fact that most CVD chambers use RPS cleaning system, so the cleaning time could be identified by FTIR endpoint detector, but both the reliability and the feedback are poor.
A solution could be to use APC to collect all the process parameters that could be related to the cleaning time through a fault detection and classification (FDC) system; study an algorithm able to both correlate these parameters to the chamber cleaning time and predict the theoretical cleaning time; and create a control strategy to monitor the chamber cleaning time wafer by wafer and, through a run-to-run framework, provide feedback for the next cleaning cycle. This analysis can be deployed on both 200 and 300 mm platforms.
Correlation with process/hardware parameters
In all dielectric CVD processes, the periodic cleaning of the equipment chamber surfaces is performed at constant pressure. Nevertheless, during chamber cleaning, the reaction between fluorinated gases and silicon oxide influences the pressure inside the chamber until the reaction is completed. A throttle valve is used to control pressure excursions. This valve changes its position according to pressure increases and decreases (Fig. 1).
| 1. During cleaning, the throttle valve (TV) controls pressure excursions in the process chamber. Pmax and TVmax indicate effective chamber cleaning. |
Comparing both trends, it is possible to understand the cleaning mechanism inside the chamber:
- The maximum value for chamber pressure (Pmax) and throttle valve (TVmax) are reached when the reaction is most effective in terms of chamber cleaning.
- When all silicon oxide has been removed from the wall, the absence of reaction inside the chamber is indicated by a plateau in the throttle valve curve.
TVmax and Pmax occur at different times. The difference is directly linked to the throttle valve mechanism, which aims to maintain the pressure setpoint inside the chamber throughout the cleaning process cycle.
Furthermore, on different chambers, for the same cleaning process, the values for Pmax and TVmax are unique, while the time when they occur can be different. The factors that can influence Pmax and TVmax include pumping efficiency, process kit status, chamber lifetime, fluorine ion generator type (RF or RPS), andthe amount of silicon oxide deposited on the walls.
In this case study, we chose the two most common parameters that influence the cleaning process: chamber pressure and throttle valve step position. Note that other parameters could be used and studied in relationship with the chamber cleaning process, such as foreline pressure, reflected power on RF fluorine generators, impedance, etc.
FDC simulation, algorithm
The starting point, to elaborate both the method and algorithm, is to study the pressure curve during the chamber cleaning process. We chose this because an unequivocal correspondence can be established between the chamber pressure and chamber cleaning time, while the TV step position can be influenced by other hardware parameters. In fact, the shape of the TV step position during cleaning is strictly related to the fluorine generator.
We analyzed the periodic cleaning of two different processes using an RPS (Process 1) and a microwave generator (Process 2), which demonstrated that the maximum chamber pressure is reached later in the microwave equipped systems. As per the analysis on monitored algorithms calculated on chamber pressure, the maximum value fits and represents well both processes.
The monitoring was conducted on three systems performing Process 1 (Systems A, B and C) and one system performing Process 2 (System D). The Table reports the time when the maximum of chamber pressure, Tmax, was reached. For Process 1, the time distribution is centered on 20–25 sec, while for Process 2, it is centered on 30 sec.
As defined in the next section, the fluorine ions generator strongly influences the time when the maximum pressure is achieved. This can be demonstrated by comparing systems with different fluorine generators and the same process (Fig. 2). Taking into account that the following study can be applied to all deposition processes, this work will focus attention on the systems equipped with RPS generators performing Process 1.
Algorithm
The theoretical cleaning time is defined as:
T = TPMax + C
where TPMax is the time when the Tmax is reached, and C is a constant. The constant is calculated by comparing chamber pressure and throttle valve values when the reaction is completed (Fig. 1). For Process 1, C has been set at 15 sec. The same method could be applied to the others processes.
In all DCVD systems, a periodic manual adjustment of chamber cleaning time is usually performed after process tests results. Some analyses have been performed, and they have shown that the new cleaning time suggested from manual check and tests is the same of that suggested from the model described in the equation. Figure 3 shows that the wafer-to-wafer model follows the clean time manual adjustment.
| 3. The clean time suggested from manual checks compares well with the theoretical time by the FDC model. |
Control, feedback
Once we defined how to calculate the theoretical cleaning time, we required a method to verify and check this value: the control and feedback of the cleaning time.
Figure 4 shows how the control and feedback mechanism works. The data transfer block, D1, performs the data collection in three steps:
- Chamber pressure and TV step position are collected during cleaning, n, by the FDC system.
- The FDC system elaborates the algorithm to calculate the cleaning time (An) for cleaning, n.
- The real cleaning time value is collected in a statistical process control (SPC) chart, where the control limits are set.
If the new calculated value for cleaning time is under control, it will be sent to a run-to-run framework (data transfer D2) to calculate the value for the feedback; otherwise, a preventive action will be sent to the host (e-mail to the users, down...). D2 then feeds the correct cleaning time to be used for next periodic cleaning. This operation can be divided in three more steps:
- If the cleaning time value calculated in D1 (An) is under control, the value will be sent to an APC database.
- An algorithm calculates the new value (An+1) for periodic cleaning, n+1.
- A feedback to the machine will take place if the defined ties are satisfied.
Figure 5 represents a typical workflow that could be used for a wafer-to-wafer cleaning time closed-loop control in feedback.
| 5. Closed-loop control of chamber cleaning time with feedback allows downtime reduction and a decrease in ad-hoc tests to determine clean times. |
Conclusions
The importance of the in situ chamber cleaning step on the dielectric CVD oxide deposition systems is well established. A comprehensive analysis of the cleaning step duration includes direct process issues, such as cleaning time. Because all of the relevant process factors (i.e., tool type, film, analysis methods) have not commonly been held constant, it is typically not straightforward to establish a relationship among all process factors.
We reported on a new method for the cleaning time monitoring and adjustment based on interfaced FDC and closed-loop control systems.
The benefits of this approach in cleaning time calculation include a reduction in tests, because no ad-hoc test is required to determine cleaning times; yield improvement, because the model is able to catch anomalous drifts in the cleaning time; and downtime reduction because of run-to-run closed-loop control, which allows cleaning time adjustment in real time. This reduces the troubleshooting related to the correct clean times and focuses the priority from the hardware point of view (process kit lifetime, powder inside the pipeline or grown on the throttle valve, etc.). In addition, the model can be equally applied to 200 and 300 mm processes.
| Author Information |
| Francesco La Spada has been working for STMicroelectronics since 1998 as a process engineer in the dielectric CVD group. He holds a degree in physics from Messina University in Italy. Email: francesco.la-spada@st.com |
| Rosaria Politi has been working for STMicroelectronics since 2000 as a photolithography process engineer. She previously worked for three years as a process control engineer in charge of FDC/APC development in the CVD area. She holds a degree in chemistry (chemical-physics specialization) from Catania University in Italy. Email: rosaria.politi@st.com |