A Step Up for High-k CMOS

Sematech, a consortium of leading semiconductor manufacturers, began operations in 1988 in Austin, Texas, with the goal of improving equipment productivity. As Sematech expanded to conduct cooperative R&D with a global network of industry, government and academic partners, its objective broadened to speed the development of innovative technologies that ultimately advanced productivity and lowered costs.

Of the 60 major project areas being investigated today front-end processes (FEP) command much attention. One focus is on high-k dielectrics and metal gates, which may serve as a key scaling knob. However, controlling the threshold voltage (V_t), particularly of PMOS gate stacks, had been thought by some to be a near insurmountable challenge, noted Raj Jammy, director of FEP at Sematech. This has changed. "The scalability of CMOS gate dielectrics has been infused with new life by the introduction of manufacturable, performance-boosting new materials," Jammy said.

1. The TEM cross-section of an 80 nm SiGe PMOS transistor demonstrated threshold voltage (Vt) control suitable for fabrication of a high-performance high-k CMOS device.

High-performance high-k CMOS

The ability to control V_t is a critical factor in determining the level of performance of semiconductor devices. In high-k materials, a temperature sensitive work function (WF) has traditionally been used to successfully tune the V_t of metal electrodes. However, despite countless research hours, one major problem has remained: Controlling V_t in PMOS devices, according to H. Rusty Harris, a project manager in FEP.

A new approach taken by the FEP researchers veers away from strictly relying on the metal WF to modulate PMOS V_t, and instead adds a method of engineering the band gap of the substrate.

According to the V_t equation, two knobs are available to device designers to control V_t: increasing the WF of the metal or decreasing the substrate band gap, thus adding to the range of suitable materials. Silicon germanium (SiGe) was selected as the substrate material, grown epitaxially on silicon (Fig. 2). The addition of germanium changes the band gap and makes it easier to attain an inversion charge, which facilitates reaching the target V_t. SiGe also has higher hole mobility than silicon, which in PMOS can result in an inherently higher drive current. Capacitance-voltage and current-voltage curves of PMOS channels containing >10% SiGe suggest a V_t downward shift of ~300 mV and a significantly higher drive current relative to silicon.

2. The data suggests that the addition of SiGe, as well as a number of other metals, to a PMOS channel provides an across the board shift in Vt of 250-300 mV.

To establish efficacy, an 80 nm dual-channel CMOS scheme successfully combined the SiGe PMOS gate with known NMOS solutions. A lanthanum (La) containing hafnium-oxide NMOS gate stack was deposited and etched using a hard mask. Then, a selective epitaxy of >10% SiGe was grown on the slightly recessed PMOS silicon. The PMOS gate stack was then similarly deposited and masked on the SiGe. After removal of the PMOS gate from the top of the NMOS mask, the hard masks were removed and polysilicon deposited. At this point, a standard planar CMOS process was followed with a typical 1070°C activation anneal.

The results proved to be comparable with those of polysilicon-based devices. The SiGe PMOS channel was crystalline-registered to the silicon, Harris said, denoting the absence of short-causing dislocations and turning defects. Both NMOS and PMOS channels had symmetric I–V curves and subthreshold slopes <90 mV/dec. The drainage-induced barrier lowering (DIBL) between silicon and SiGe was just about the same, an indication that the off-state leakage current is comparable in the two channels.

Targeted for the advanced 45 nm technology node and beyond, the band-engineered high-k CMOS approach using conventional gate-first high-temperature processing "is one of the first true bridging demonstrations of alternate channel materials that have the potential of going to manufacturing," Harris said.

Seeking answers to performance

A highly scaled high-k metal gate nFET fabricated in a gate-first process flow that includes a 1070°C anneal was demonstrated by Sematech's FEP group. The traditional SiO₂/polysilicon gate was replaced with HfO₂ doped with the rare earth (RE) element lanthanum. The 80 nm nFET exhibited high mobility, 85% of comparable SiO₂/polysilicon gate devices, 9 Å effective oxide thickness (EOT), bias temperature instability of < 20 mV, and V_t of 0.3 V.

While the results are impressive, they cannot be explained solely by the commonly held view that a shift in the WF, and therefore control of the V_t, can be achieved by selecting an appropriate metal electrode and taking into account its interfacial interaction with the high-k dielectric.

Needing to understand the mechanism at work, "We hypothesized that a dipole moment is formed in the high-k gate stack and is responsible for tuning the threshold voltage," said Paul Kirsch, FEP dielectrics group leader. If this hypothesis is correct, he continued, then we would expect the V_t to be dependent on the electronegativity and cationic radius (size) of the dopant.

Subsequent Fourier transform infrared (FTIR) measurements showed RE-O-Si bonding, and verified that the dopants diffuse through the high-k layer reaching the SiO_x interface, where they are thought to form the critical dipole that tunes the V_t. Several dopant types were integrated into HfO₂/metal gate transistors, including strontium oxide, erbium oxide, scandium oxide, lanthanum oxide, and erbium plus scandium oxide. The hypothesis is supported by the results, showing that dopants of different electronegativities move the V_t over a wide range, from V_t=0.1–0.5 V (Fig. 3).

3. Threshold voltage is demonstrated to shift generally ~300 mV with Vt of SrO<Er<Sc+Er<LaO<Sc. LaO denotes an optimized LaO process.

From a dipole moment model, the dipole moment is equal to the charge multiplied by the distance between the RE atoms and its oxygen-bonding partner, RE-O. Therefore, the phenomena can be explained by the relatively larger dipole moment of RE-O (less electronegative with larger cationic radius) to that of Hf-O. The net dipole moment vector thus points from SiO_x toward the high-k dielectric, and shifts the effective metal WF in the desired direction toward the silicon conduction band.

There are many implications of this study. With V_t shifts away from the undesirable midgap value toward the silicon conduction band edge, even after undergoing thermal treatment to >1000°C, achieving a targeted nFET V_t may be a matter of selecting the right RE dopant.

PMOS solutions for low power

The dipole moment concept has also opened the way to a straightforward PMOS solution for low-power applications. Demonstrated for the first time by Huang Chun Wen and FEP co-workers was the formation of a metal AlN PMOS gate electrode on a high-k gate dielectric stack that resulted in a transistor with a high effective WF of ~5 eV and a low V_t value of ~ 0.35 V.

Aluminum is known to create shifts in the WF; however, depositing aluminum oxide (AlO) on top of a high-k dielectric layer has also been shown to degrade reliability and increase the EOT by ~0.3–0.5 nm. Focusing on the benefits of aluminum, the FEP group sought to circumvent EOT issues by incorporating aluminum directly into the gate electrode. With a subsequent high-temperature anneal, aluminum diffuses through the HfSiO_x high-k layer to the SiO₂ interface. And once the aluminum reaches the SiO₂ interface, the V_t begins to shift.

The increase in the effective WF and V_t control were verified with backside secondary ion mass spectroscopy (SIMS). As previously described, the increase is attributed to a dipole formation at the interface between the high-k layer and SiO₂ beneath. A low EOT was also sustained because of the critically small amount of aluminum at the interface — less than a monolayer — said Byoung Hun Lee, gate stack program manager. From a manufacturing standpoint, the FEP team demonstrated that controlling the amount and concentration of aluminum in the electrode can easily be achieved to within a monolayer accuracy with current physical vapor deposition (PVD) technologies.

Previously, high effective WFs have been obtained on SiO₂ dielectrics using TiAlN and TaAlN electrodes. However, when applied to PMOS high-k gate electrodes, these materials produced effective WFs much lower than 5.0 eV, the level typically needed for low-power applications. After testing a number of metals, MoAlN was identified as a very stable, high-performing electrode, producing the required effective WF shifts (Fig. 4).

4. The I-V curves suggest that MoAlN can produce low Vt electrodes relative to TaN, the gap between the curves indicating the difference in effective work function between the two materials.

To achieve band edge effective WF metal that can be used for PMOS has required going beyond selecting a material with a high WF. It has meant evaluating the gate stack through materials and process integration to the crucial role the high-k/SiO₂ interface plays in controlling V_t. As with EOT and effective k (k_eff), "We can no longer think of metal electrodes in terms of a single work function, but of an effective work function representing the entire gate stack," Lee said.

With an eye to the future, Jammy asks, "How do you scale these gate stacks to 22 nm technologies without losing performance or introduce additional problems like charge trapping in the films that would affect the stability and reliability of the devices?" He further ponders the need for flexible deposition, integration, metrology and characterization solutions when dealing with new materials for future needs. But as the industry well knows, all workable solutions begin with asking the right questions.