Sematech 3-D IC Workshop Considers Thermal, Design Issues
Staff -- Semiconductor International, 9/24/2007 1:48:00 PM
Sematech is sponsoring a workshop on 3-D ICs Oct. 11-12 in Albany, N.Y. The workshop will consider design and thermal challenges for chips connected with through-silicon vias (TSVs).
The workshop’s program begins with an overview of 3-D thermal and design issues, with an introduction by Phil Garrou from Microelectronic Consultants of North Carolina, followed by Mike Ignatowski, IBM (White Plains, N.Y.), who will speak on the “Challenges and Opportunities for Exploiting 3-D Technology in System Designs.” Takafumi Fukushima from Tohoku University will discuss “Thermal Issues of 3-D ICs.”
The second session will consider applications, starting with a presentation by John Magerlein, IBM, on “Thermal Limits and Approaches for 3D Chip Structures,” followed by Bob Jones from Freescale Semiconductor Inc. speaking on “Technology, Design and Applications of 3-D Integration.” Muhannad Bakir, Georgia Institute of Technology, will discuss “Limits and Opportunities for Heat Removal and Power Delivery to Gigascale Systems,” followed by Michael Fritze, DARPA, and Michael Steer, North Carolina State University, discussing “Thermal Challenges in DARPA’s 3-D IC Technology Portfolio.”
A session on modeling, design and architecture begins with Ruchir Puri, IBM, considering “3-D Design and CAD Challenges,” followed by Yuan Xie, Penn State University, on “Design Space Exploration for 3-D Architectures,” and Jason Cong, UCLA, on “Thermal-Aware Physical Design for 3D ICs.”
A session on thermal characterization and management begins with Darvin Edwards, Texas Instruments, speaking on “Thermal Management for Low Cost Consumer Products,” followed by Tan Chuan Seng, Nanyang Technological University-Singapore, on “Heat Removal Enhancement of 3-D Interconnects Using Copper Wafer Bonding,” Rajiv Joshi, IBM, on “Thermal Analysis of Bonded Wafers,” and Seri Lee, Nextreme, on “Thermoelectric Cooling for 3-D Chip Stacks.”
“This approach has many potential advantages — improved electrical performance, lower power consumption, integration of different device types, and lower cost,” said Larry Smith, a Sematech engineer and workshop chair, adding that the approach also presents “many new challenges to the design community, including how to deal with higher power densities.”
The workshop is being held in conjunction with the Advanced Metallization Conference Oct. 9-11 at the Albany Marriott Hotel. It is being cosponsored by the ACM/SIGDA Physical Design Technical Committee.
