How Well Can Yield Be Predicted?

Yield prediction is one of the cornerstones of design for manufacturing (DFM). But it's much more than that. "Our ability to accurately predict yield is really our economic model," said Dan Armbrust, vice president of 300 mm Semiconductor Operations for IBM's Systems and Technology Group (East Fishkill, N.Y.). Armbrust was one of the three panelists that discussed the state of DFM at a yield panel held at SEMICON West 2007. He was joined by Anantha Sethuraman, vice president of DFM Solutions at Synopsys (Mountain View, Calif.), and Chris Progler, CTO of Photronics (Brookfield, Conn.).

IBM, as a foundry, device manufacturer and systems house, sees a diversity of design styles, design complexities, chip sizes and so forth. "We have been able to predict, at least for prototypes, designs that have worked right over 90% of the time. If not, there is a problem with the product owner or the fab, and we have to figure it out and solve it," Armbrust said.

Sethuraman said that design and manufacturing really started to come together at the transition from the 90 nm node to the 65 nm node. "Now we're doing litho compliance checking, LCC, which means we can determine whether we can really print the design," he said. "At 65, there was a lot of new learning in simulation and mask making, which is going to help at 45 and 32 nm. But there are also new challenges and variability at 45 and 32 nm, which will keep us busy."

Tying defects to actual electrical problems on the chip is difficult. Of course, a good percentage of defects will not impact yield, while others will. "From a maskmaker's perspective, our studies show that on one design, 10-20% of defects will not impact yield, but this will not be true for another device where 80–90% of the defects will be important," Progler said.

Armbrust added, "In semi manufacturing, you're overwhelmed with data. For instance, any time you run a design through for rules checking and printability, you get overwhelmed with near misses and potential concerns. So we take a subset and look at them, but there's only so much of this that you can do. Understanding the critical design elements can narrow that field dramatically, and that's huge." He also talked about the massive amounts of inspection data. "If we can get design intent, then we can look specifically at the defects that most impact the design, rather than treating them as equally suspect."

At 32 nm, Armbrust explained that little performance advantage comes from shrinks due to power issues. "The most successful companies are trying to innovate at a different level. You can sort out your product and run portions at different voltages at the system level, if you think that through early in the product design. Something like timing simulations is very difficult, especially if you combine IP from different companies. There are sophisticated delays that can be introduced into the functionality and testability of the product and still get good yields."

From the design side, Sethuraman said that both restricted design rules and modeling will be needed at 32 nm. "We need to do both because if we put everything under tight restrictions, we might stifle the creativity of designers."

Synopsys tracks new designs at the various technology nodes. They have tracked more than 200 tape-outs at 65 nm and 10 tape-outs at 45 nm. Though some companies are doing designs at 32 nm, they had no hard numbers to report yet.

Talking DFM were (left to right) moderator Ron Wilson of EDN, Dan Armbrust of IBM, Anantha Sethuraman of Synopsys, Chris Progler of Photronics and Peter Singer of Semiconductor International.

Sethuraman also addressed the predictability of yield. Because a manufacturer has "n-1" manufacturing data, this can be used to predict yield with a high accuracy. "But accuracy is a moving target," he said.

Progler talked about the fact that the mask is the first time a design makes its transition from software to hardware. "You can measure many things on these first masks, and I don't think this ability is leveraged as heavily as it could be," he stated. At the same time, he said that the most successful designs today are more memory-like. By altering the design to give it more regularity, the chance of successful yield is going to be higher. The most extreme example of this is NAND flash memory. Regular designs will be an important enabler for double patterning (DP), which Progler expects is still three years out for mainstream adoption. Armbrust said DP will have to be used at 32 nm.

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