Advanced Masks Help Keep Photolithography Alive

In an industry driven increasingly by economic considerations, the right technology for the job may not be the one with the highest capabilities. In fact, semiconductor manufacturing as a whole will almost always make do with the current technology until it just won't work anymore. And just as lithographers have found ways to keep photolithography as the workhorse of the industry rather than move to more expensive alternatives, the photomask industry within that scheme has been able to get by without making drastic changes to the landscape.

As Chris Progler, CTO at maskmaker Photronics Inc. (Brookfield, Conn.), put it, "Mask technology isn't changing dramatically. It's just kind of another turn of the screw, if you will, on specs and things like that." It's certainly getting tougher, and it's pushing the limits of the infrastructure in some ways, he said, but it is one primarily of evolutionary changes.

Optical proximity correction (OPC) has matured and improved to a degree that the (in many ways) technically superior strong phase-shifting masks (PSMs) that have been developed along the way just haven't been needed. The industry, for the most part, has found ways to get the image quality necessary without using such tools as alternating phase-shift masks (altPSMs), according to Franklin Kalk, CTO for Toppan Photomasks Inc. (Round Rock, Texas). "If they truly needed them, we would be building them. The fact is that they're not really necessary," he said. "At every node, one or maybe a few customers use strong shifters. But then those people even can figure out ways to maybe use half-tone instead, or OPC, and then overcome the need for the strong shifter and move away from it."

Kalk told of a situation in which one customer used strong shifters at the 130 nm node, then dropped them at 90 nm — even while staying with a KrF (248 nm) exposure tool. "Now, there was a change in NA; the tools got a little bit more exotic," he said. "But it wasn't a quantum leap in k₁. But they switched. They just found better ways to do their imaging."

Today, without using strong phase shifters, foundries such as Taiwan Semiconductor Manufacturing Corp. (TSMC, Hsinchu, Taiwan) or UMC (Hsinchu, Taiwan) can achieve 65 nm node printing as well as the IDMs using them, according to Cliff Ma, director of business development, design to silicon, for Mentor Graphics Corp. (San Jose). "At 65, clearly the alternating phase shift was overkill," he said. "The cost was way too expensive to make, and the benefit out of that is not justifiable."

Instead, OPC and other resolution enhancement techniques (RETs) have been maturing. "People have found a way to do OPC more quickly or more elegantly, and of course we can't minimize the impact that argon fluoride [193 nm] exposure tools have had," Kalk said. "And now with very high numerical apertures [NAs] coming in with immersion, again it mitigates the need to go to a more exotic mask architecture."

1. Advanced photomasks are relying on aggressive OPC to achieve improved imaging capabilities. Shown here is an advanced mask for mass memory device production. (Source: Toppan Printing Co. Ltd.)

All of this is not to say that things are not changing in the mask world. Indeed, several factors have made photomasks increasingly complex, not the least of which are the effects introduced with immersion lithography and the hyper-NA lithography that goes hand in hand with it. With that, the masks are getting more complicated to understand, model and analyze, noted Progler during a panel discussion at SEMICON West.¹

"There are so-called electromagnetic effects at the mask that exist now with those kind of exposure approaches that just didn't exist or didn't matter previously," Progler said. "An analogy I can draw is a mask used to be like flying in a plane over a mountain range. And basically you just cared if things looked flat, and you see this here and that here. With hyper-NA, now you've got to get down into the mask and see the rocks, and all of these things are impactful to imaging."

The effect, to some extent, is that the mask has become a much stronger optical element in the imaging system, Progler added. Therefore, simulation tools need to be upgraded to compensate, and additional data must be gathered to understand the implications.

Perhaps one of the biggest challenges with hyper-NA imaging is the effect on mask polarization, Weed said, adding that such effects will require much more in-depth simulation in terms of what and how the light interacts coming from that source. "The mask has always been the whipping boy," he said. "But because of the hyper-NA and whatnot, and the polarization effects, it's going to become a more integral part of the optical path. Within the imaging systems, you have these bazillions of lenses, and all of the curvature and the issues that are associated with the lenses. Now you're inserting this quartz, and now with the effects that used to not be important are now important. And this big slab of quartz is now integral in that whole optical path."

For the maskmaker, hyper-NA is an interesting challenge because the mask stack is different than it is for NA<1, according to Kalk. Below 1 NA, a half-tone phase shifter will typically produce a better image than a binary mask. However, at NAs well above 1, the situation is reversed. "Binary actually gives a little better imaging performance, and by that I mean, if you look at depth of focus and exposure latitude together," he said. "And the reason for that has to do with the electrical properties of the mask absorber layer."

Toppan is conducting R&D with a variety of companies to develop new mask stack technologies that would have better imaging properties for hyper-NA lithography. "What we're finding is, even in phase shift, the sort of standard 6% transmission half-tone materials, that really doesn't work that well at high NA," Kalk said. "We're finding transmissions on the order of 1 or 2% are actually working better — with the historical materials like moly silicide. But we're also looking at a variety of new materials that can maybe combine high electrical conductivity with some reasonable amount of transmission to give us better imaging." That work is probably still a couple of years away from manufacturing, he said. "But immersion is coming into manufacturing in the first half of '08, so we will make do with what is already existing for those manufacturing processes."

Even without immersion lithography in the picture, mask complexity is growing simply as a result of more aggressive OPC schemes needed to improve imaging with continued transistor scaling. The complexity itself is a challenge, but the large amounts of data that are produced as a result also create their own challenges.

At the 45 nm node, logic data volumes, in particular, are turning out to be substantially larger than first expected, Kalk said. It is typical that maskmakers see giant data volumes when a node first hits, he explained, because chipmakers are overly aggressive with OPC. But when they see huge write times and, in turn, the high mask costs, they tend to rethink their OPC strategies, cutting a few corners here and there. "They'll become less aggressive with the OPC, maybe test the lithography platform a little bit more, and the write times come way down on subsequent writes," Kalk said.

Although the trend has been for mask write times on e-beam writers to remain relatively constant since 2000 (with tools making strides to offset increased data volumes), that could run out of steam at 45 nm logic, Kalk said. "We believe the data volume is going to start to grow now disproportionately relative to the writing speed of the tools. So we think the write times are probably going to go up. And that will happen short-term, over the next couple years. So we're working really hard with the writing tool suppliers as well as with our customers to balance out the need for good imaging in the fab and also to try to get better writing speeds out of our tools."

One way to reduce writing times is to reduce the shot counts that a mask writer must perform for any given design, Mentor's Ma noted. "The shot count relates to the data, which is OPC data," he said. "If the OPC data is not very well optimized for that, you're going to have extra shot counts without getting any real benefits."

With OPC getting so aggressive, the EDA companies are also looking for the best way to transfer the increased data volumes in a timely manner; to hold down access and transfer times as the data travels from one server to the next. "It can kill a process; it takes forever," Weed said.

Customers are asking for the mask data preparation time to be essentially zero, according to Weed. That may sound like quite the trick, but it is done by burying mask data prep within other processes. "If you have one process run that takes, say, 24 hours on OPC. If then you typically would do your mask data prep after that, what you can do is you pipeline it...and it's done while your OPC is being done," Weed said. "So we have a technology that we're working with some major customers, and it's been implemented and it works. As the OPC is done, it sends those little files.... As the OPC finishes for a portion of the chip, it will send those ahead, and it will work on those individual pieces and it will complete them. So by the time you're done with the OPC, you're done with the fracturing."

Along with this sort of scheme, EDA vendors are looking for the best way to get the data transferred quickly. Some are relying on custom hardware accelerators, while others feel that help can come in the form of improved general processing capability. "The capability of any of these general-purpose microprocessors are going to be far superior in the not-too-distant future compared to these very specific custom pieces of hardware — the accelerator hardware, which is specific to a certain application, so if you change your application, you need more hardware," Weed said. "We believe that if you have and can work with the existing infrastructure that is in the market, and have a capability that is very scalable in terms of CPUs, then in the long run, you'll be better off and have a better ROI than these custom hardware boxes." Synopsys has proven out that data (Fig. 2 ).

2. Although there are hardware-based accelerator solutions that can transfer mask data quickly, they do not necessarily provide the best ROI over optimized software combined with general-purpose hardware systems. This comparison shows a general-purpose microprocessor solution (using Proteus) and several custom acceleration options that have been price-normalized to it, with the lower numbers providing a better ROI. Fast Fourier transform (FFT) is used as the common means of evaluation. (Source: Synopsys Inc.)

Where mask complexity will increase further and transfer times will become even more crucial is with double patterning — a variety of schemes that essentially split a design layer into two masks to improve k₁ and achieve tighter pitches on the final wafer.

The EDA vendors certainly have their eyes on double patterning, and are working on refining their splitting algorithms to minimize complexity and, therefore, alleviate potential data transfer bottlenecks. "It's kind of like the four- or five-color problem in terms of the world map. What's the minimum number of colors that it takes to color every country in the world without any two adjacent colors being the same? That's the type of algorithm that the guys have to work on," Weed said. "And having done that for the darkfield alternating aperture, the next step in terms of what's required in terms of the pitch splitting and whatnot, it's not a big step. So we are keeping our eye on the market. We have people that are working on the dual patterning."

One question still up in the air, however, is exactly where the pattern splitting will be carried out. One possibility is that it will be done by the maskmaker, according to Kalk. "We already do OPC, but pattern splitting is another level of complexity, another level of difficulty," he said. "But it's actually worked out pretty well so far. The nice thing about having it done by the mask supplier is that it actually keeps the cycle time relatively short in synthesizing the mask data, and in building the mask as well."

Not only could this scenario reduce cycle time by circumventing the ever-growing data transfer times, but because the maskmaker is more familiar with its own processes, it may also actually be able to realize a mask that will image better for the wafer fab. Still, the maskmakers will need help from the EDA side in creating the tools necessary to get the job done effectively.

Pattern splitting can be done now, but EDA tool vendors will need to do some more work to do the splitting effectively and quickly. And the splitting is likely to become even more complex over time, Kalk mentioned. "Let's assume it works well. What's to stop us from going to triple or quadruple patterning if it might mitigate the need to go to something that's more costly or more complex? We don't really know when EUV is truly going to be ready, for example. So it could be that there will be much more elegant pattern splitting requirements four or five years out."

But first, chipmakers will decide when they will likely need to make the leap to double patterning. Double patterning is being widely considered for 32 nm manufacturing, although some think they may still be able to get by without it.

"I think maybe for some manufacturers, at 32 they might need it, but for most, probably not," Ma said. "Because it's way, way too expensive."

"I think you'll see more of it for 32," Progler said. "I don't think you'll see it as mainstream. Foundries, I personally don't believe they're going to use a lot of it. But I think you'll see more double patterning, particularly on the memory side, for sure, for that node."

Speaking at the yield panel at SEMICON West, Dan Armbrust, vice president of 300 mm semiconductor operations for IBM's Systems and Technology Group (East Fishkill, N.Y.), spoke much more unequivocally. "We see it as a reality for 32," he said. "I'm not sure how we're going to be able to print the images any other way, unless someone has a sleek new litho tool."

That "sleek new tool" might be extreme ultraviolet (EUV) lithography, but that's just not coming quickly enough for some chipmakers. But work needs to be done on double patterning to make sure the infrastructure is prepared for that as well. Asked during the panel discussion whether the industry is really going to be ready for double patterning, Progler responded, "Double patterning, from the mask side and litho side, there's still some challenges there to do it for a wide range of devices. I mean, some simple designs, regular designs, people are already doing double patterning, to some extent, in production. But to really make it invasive and generally applicable, I think there is a roadmap there, with, I would say, three or four tough engineering challenges."

Two key challenges are how best to split the pattern and the tight overlay capabilities that will be required from the toolmakers. "I think you need to do a refresh on some equipment so that it's viable, so that's at least three years, I mean to really do it well, to get the full double patterning entitlement, I call it, which means really pitch splitting, all those sorts of things," Progler said. "But to get the full, I'll call it 'node entitlement' of double patterning, there's infrastructure that needs to come on the litho side to make that productive and viable."

Pattern splitting is not a trivial task, Kalk noted. "It requires that you're able to take the data, extract the two or more patterns — however many mask levels you're going to have, but let's say two. So extract those two levels, make sure that when you put them back together you're going to get the right answer, but then you have to build two masks from that," he said, adding that that leads to the other challenge, which is the overlay of the two masks.

"In mask manufacturing, we've never really been faced with an overlay tolerance nearly as tight as what we're seeing for double patterning," he said. Toppan has been working with mask writer suppliers, as well as metrology tool suppliers, for improved measurement capabilities, and with exposure tool suppliers to see what today's capabilities are. "I'm happy to report we're a lot closer than we thought we'd be at this point," Kalk said. "Within three years, I think we'll be in very good shape on double patterning."

What some are saying may need to happen to improve the lithography process window — whether for double patterning or not — is to simplify circuit designs, thereby making them more lithography-friendly. Photronics, through the variety of design data coming through its shop, has seen what Progler considers an encouraging trend in this respect. "The biggest thing we've noticed is the most successful designs seem to be much more regular, more memory-like," he said. "Companies that are really yielding well are accepting this idea of design rule restrictions, make things more regular, make them look more like arrays, particularly for gate-level and high-performance processors."

Fewer features and pitches is a great trend for the industry, Progler said. "People can still get the functionality and density out of their devices, but move towards more regular designs, a fewer set of structures and features. This definitely is going to help, certainly from a lithography and characterization side."

"It sounds almost too simple — to make it more simple, like memory," Weed said. "But memory guys can ramp yield up like gangbusters. And it's because it's regular, there aren't a lot of changes, and once you master that, you can replicate that across the board."

NAND flash is the ultimate demonstration of this trend, Progler pointed out. Patterns are extremely regular — basically a set of nested lines. NAND devices are printed with extremely aggressive k factors, he added. "Almost theoretical limits to some of the highest yields in the industry, partially because of the way the device is structured, but largely because it's a very, very simple layout, and you can really ramp manufacturing on something like that very quickly," he said.

Some of what can be done with widening lithography process windows involves putting tighter restrictions on designers to simplify manufacturing. IBM has seen this trend both as a chipmaker and as a foundry, according to Armbrust. "Especially being an integrated manufacturer, we've been able to be more aggressive with some of the restrictions on our internal designs because we have a history of what that IP looks like; it's portability issues are understood," he said. "And by putting more restrictions in place, we've actually had extremely robust results from that."

That isn't always achievable in all sectors of the industry, however, because of the desire to be compatible with industry standards, Armbrust explained. But that could change. "I think maybe an interesting point moving forward is the foundries are defining the industry standards and what's acceptable within design practices to a great degree," he said. "I think it's a challenge for them, because the degree that they want to clamp down on these, they restrict a whole variety of products and designs. I think it's difficult for them to do."

But if chipmakers can get in front of the issues and challenges, they have the opportunity to incorporate restrictions that make sense, Armbrust said. "The question is: How fast as an industry can we move, given how we're currently structured today?"