Predicting the Future in the Past

In late 2007, yet another edition of the International Technology Roadmap for Semiconductors (ITRS) is nearing completion. This will be the eighth version of the roadmap, if my counting is correct. Rummaging around my cluttered office, I managed to find a copy of the first "official" roadmap, the SIA's Semiconductor Technology Workshop Conclusions, published in 1993 but based on a workshop held in Irving, Texas, in November 1992 (the document wasn't called a "roadmap" until its second edition in 1994). The stated goal of the workshop was to "...create a common vision of the course of semiconductor technology over the next 15 years." The workshop also had an explicitly nationalistic goal of helping the U.S. semiconductor industry against foreign competition, but that goal disappeared when the National Technology Roadmap for Semiconductors went international in 1999. Here it is, 15 years later, and we are still projecting semiconductor technology far into the future. It might be instructive to examine these past predictions from 1992 to see if there is anything to be learned from the way the future looked in the past.

As Gordon Moore himself said in 1975, Moore's Law has historically been comprised of three factors: decreasing feature size, increasing chip area, and improving device "cleverness." Extrapolation of the historical trends for each of these factors was the basis for this first roadmap. How did the industry perform relative to these projections? Feature size has scaled faster than expected, and we are now about one full generation ahead of "schedule" (Table ). Likewise, chip speed is about four times faster than expected (due, in large part, to the faster shrinking of feature size), although it is now clear that clock speed will no longer increase at these historical rates. Chip size, however, has not even come close to meeting expectations. While the leading-edge memory and logic products have been increasing in size at the time of first demonstration, volume manufacturing of those parts invariable shrinks die area to the common 100–300 mm² size range, and these production die sizes are expected to remain flat going into the future. The economics of IC manufacturing puts a steep premium on chip area, so feature size scaling is significantly favored over chip area scaling. Design compaction, where the same transistors are more cleverly arranged to achieve smaller die area, is one of the primary goals driving advances in EDA software, although lately it is hard to claim that we have been able to keep up with historical improvements in this area.

"Lithography is both the dominant cost factor in wafer processing and the driving technology for increasing chip functionality and, hence, is the primary pacing technology for industry progress." This statement from the 1992 workshop is only more true today. Shrinking feature sizes are now a larger fraction of the generational productivity improvements (lower cost per function) that drive Moore's Law, and lithography has certainly not been dropping in cost. Thus, any projection of the roadmap into the future must, by necessity, assume that lithography will scale faster in feature size than in cost. While the other scaling trends of the past have significantly slowed, lithography scaling has kept Moore's Law and the industry on track.

How long can lithography keep up this pace? Probably not for much longer, and certainly not for the 15-year horizon of the upcoming 2007 roadmap. But, of course, ITRS working groups will have no choice but to assume that all barriers will be overcome and lithography will continue on its designated path toward 10 nm half-pitch. As the former head of lithography research at a major semiconductor manufacturer once told me, "It's our job to be running as fast as we can when we hit the brick wall." Others may be worrying (or trying hard not to worry) about where the brick wall is, but us lithographers just keep running.