Japanese Chipmakers Unveil Memory/Transistor Tech

Several Japanese companies announced major advancements at this year's VLSI Technology and Circuits Symposium, held June 12-16 in Kyoto, Japan. Toshiba (Tokyo) announced a 3-D cell array that increases density with existing process technology. Fujitsu (Tokyo) unveiled a new low-power/high-performance 45 nm platform, while Renesas Technology (Tokyo) debuted a low-cost, high-performance transistor technology for microprocessors and system-on-a-chip (SoC).

The Toshiba announcement was perhaps the most interesting in that it did not rely on advances in process technology, but instead a new 3-D memory cell array structure. The new structure (Figure ) enhances cell density and data capacity, with minimal increase in the chip die size. In the new structure, pillars of stacked memory elements pass vertically through multi-stacked layers of electrode material and use shared peripheral circuits.

Toshiba introduced a 3-D memory cell array structure based on innovations in stacking. The new array is easier to fabricate and does not produce much of an increase in the overall chip area, as peripheral circuits are shared by several silicon pillars.

Typically, advances in memory density reflect advances in process technology. Toshiba's new approach is based on innovations in the stacking process. Existing memory stacking technologies simply stack 2-D memory array on top of another, repeating the same set of processes. While this achieves increased memory cell density, it makes the manufacturing process longer and more complex. The new array increases memory cell density, is easier to fabricate, and does not produce a large increase in chip area, as the peripheral circuits are shared by several silicon pillars.

Toshiba's etching technology drives a through-hole down a stacked substrate (i.e., a multi-layer sandwich of gate electrodes and insulator films). Pillars of lightly doped silicon with impurities are deposited to fill in the holes. The gate electrode wraps around the silicon pillar at even intervals, and a pre-formed nitride film for data retention, set in each joint, functions as a NAND cell. Toshiba's method has a silicon-oxide-nitride-oxide-silicon (SONOS) structure, and the electrical charge is held in the silicon-nitride film.

Toshiba's array increases density without increasing chip dimension, as the number of connected elements increases in direct proportion to stack height. For example, a 32-layer stack realizes 10× the integration of a standard chip formed with the same generation of technology. Toshiba will further develop this elemental technology to the level where it matches current structures in terms of reliability.

Fujitsu's 45 nm platform, on the other hand, combines technologies for low-power consumption and high-performance interconnect. The company said that compared with previous 45 nm technologies on record, this platform reduces the leakage current that occurs when current is wasted in wait states to one-fifth that of previous levels and reduces interconnect-induced lag times by ~14%.

In addition to a millisecond “flash” anneal for the transistor source/drain (S/D) regions, Fujitsu researchers used nanoclustering silica (NCS), which has a dielectric constant (k) of 2.25. NCS is a microporous material enabling both a low dielectric value and high mechanical strength. The company introduced NCS on a partial basis beginning with the 65 nm generation. However, for 45 nm, it is using NCS not just within a given interconnect layer, but also between different layers to further reduce interconnect capacitance.

Renesas Technology is also focused on 45 nm technology, announcing what it described as an extremely high-performance transistor technology with low-cost fabrication capability for microprocessors and SoC. This technology improves the performance of complementary metal insulator semiconductor (CMIS) transistors with a proprietary hybrid structure — an advanced technology that the company previously announced in December 2006. The p-type transistor gate structure consists of two titanium nitride layers. A high-k layer, CVD-TiN layer, PVD-TiN layer, and polysilicon are stacked on a silicon substrate in that order. The PVD-TiN layer is denser than the CVD-TiN layer, so silicon diffusion into the CVD-TiN layer from the polysilicon electrode is suppressed, preventing property changes that would otherwise increase the threshold voltage. Better yet, the two TiN layers actually lower the transistor's threshold voltage by ~100 mV to a level appropriate to a low-leakage device.

An experimental chip containing transistors with a 40 nm gate length has been fabricated. Data from tests performed on this chip have confirmed top-level drive performance: 1068 µA/µm for the n-type transistor and 555 µA/µm for the p-type transistor at a 1.2 V power supply voltage.

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