Mobile and Wireless Packaging Solutions

Mobile consumer electronics markets continue to be among the largest and fastest growing semiconductor segments. Mobile phone handsets areexpected to exceed worldwide shipments of 1 billion units in 2007 and reach 1.5 billion units by 2011. Market analysis for the mobile PC market, including PDAs and smartphones, forecasts this segment to continue experiencing double-digit growth over the next several years. These markets are rapidly evolving with each generation, offering increasing feature sets and functionality or reductions in cost. Package solutions have been developed to achieve the needed levels of integration for the current generation of products, but the industry is facing challenges in maintaining the pace of innovation. Key challenges for the industry are to enable new features while still meeting the customer expectations for cost, form factor and performance. Market demands have placed a burden on manufacturing and design to achieve greater integration and miniaturization while still getting the product to market on time.

Mobile electronics packaging

This image shows a 0.8-mm-thick µPILR four-high DRAM package-on-package (PoP) stack. (Source: Tessera Inc.)

Area array package technologies, such as ball grid array (BGA) or fine-pitch BGA (FBGA), use solder balls under the package to form electrical interconnections between the package and printed wiring board (PWB). These package types allow for “fan-in” routing where interconnections can be formed underneath the packaged IC. This allows for smaller form factor packages, compared with leadframe technologies when package I/O counts exceed ~30 to 50 I/O, if the size of the IC allows for the reduction. FBGA packaging is increasingly popular and finding widespread use in mobile electronic devices. These package technologies typically have a higher cost than leadframe, but this is justifiable in situations where the form factor and interconnection density is required.

Wafer-level package (WLP) technologies offer exact die size form factors, as these packages are formed directly on the IC device itself in the wafer back-end manufacturing process. In applications where package reliability requirements can be met and the required I/O can fit within the form factor of the die without overly constraining other aspects of the interconnection, WLP may offer an attractive solution. Most WLP solutions are targeted at applications with <100 I/O and die sizes <5 × 5 mm.

To reduce the overall form factor of mobile electronic devices, various forms of 3-D packaging, including stacked die, system-in-a-package (SiP) and package-on-package (PoP) products, have evolved that allow for integrating multiple die. These solutions are being adopted with increasing popularity, and allow for the integration of different logic functions and memory in the same footprint. Common implementations stack a memory subsystem stacked die package onto a mobile processor package. The memory subsystem package typically includes some combination of NAND flash, NOR flash, SRAM or PSRAM, and mobile DRAM. Several factors must be considered when exploring options for die stacking, SiP and PoP, such as form factor, performance, cost and time to market.

There are several key advantages of the PoP configuration. Primarily, the PWB area required for mounting is significantly reduced over a side-by-side solution while providing a reduction in total package volume. PoP allows for sourcing stacked die memory packages for the top package from multiple vendors. This creates a more flexible supply chain for the manufacturer that is integrating the PoP at assembly. PoP allows for increased performance as the electrical path between logic and memory is shortened. Testing of the logic and memory packages are performed separately, improving final assembly yield.

Bottom logic package size is driven by either the area required for achieving interconnection with the PWB or the area required for mounting the processor IC plus accommodating the I/O pads for the top stacked package. In either case, pitch between solder pads becomes one of the limiting factors in determining the package size of the bottom processor package. The trend for PoP is to reduce the package pitch on both the bottom logic package and top memory package to allow for a higher interconnect density in a reduced area. This mirrors the general trend in the mobile electronics packaging industry to reduce pitch and form factor. We have developed a new interconnect technology platform called µPILR that has unique advantages for area array and PoP applications requiring a high number of interconnections with reduced interconnect pitch.

µPILR interconnect technology platform

1. SEM image of a 125-µm- high micro pin interconnect contact.

µPILR interconnects are fabricated using standard processing equipment and chemistries that are in use by semiconductor packaging substrate and PWB vendors. One method of forming the µPILR contact is by etching a trimetal material of Cu/Ni/Cu. One of the two copper layers is used for formation of the µPILR contacts. The alternate copper layer is used for formation of circuitry. The nickel layer acts as an etch barrier to allow for separate formation of circuitry and µPILR contacts. The height of the µPILR contact is determined by the thickness of the copper material from which it is formed. Typical thicknesses of copper foil that are used range from 50 to 125 µm. Once the µPILR contacts are fabricated, they are of highly uniform height because they are formed of material of uniform thickness. Various dielectric materials have been evaluated and may be used, including glass-fiber-reinforced FR-4 or BT, or polyimide.

2. A 10 ×10 × 0.4 mm pitch area array substrate with 529 I/O (dime shown for scale).

Component assembly processing for µPILR packages uses standard semiconductor assembly equipment for die placement, wire bonding and overmold. SMT attached µPILR contacts replace the BGA ball; no BGA balling process is needed for mounting these parts. This also illustrates an important attribute of this technology — no specialized tooling or equipment is required to process this technology at assembly.

High-density, small form factor PoP

The height of the encapsulated wire bond or flip-chip processor IC on the bottom package determines the standoff required for joining the top package in PoP applications. Because of the spherical shape of the solder ball, a trade-off between standoff height and BGA pitch exists when using solder balls for interconnection. The standoff height is a function of solder pad area, solder volume and package mass. As pad pitch is decreased, solder volume must be reduced to prohibit solder shorting of adjacent balls during assembly. This limits the height of the standoff that can be achieved using a solder ball-only solution (Fig. 3 ).

3. The PoP standoff height vs. package pitch and solder ball diameter.

4. SEM of a PoP interconnect cross section for 0.5 mm pitch with 420 µm standoff.

Figure 5 shows a rendering of a PoP test vehicle that is being designed to further evaluate µPILR. It uses 0.5 mm pitch for interconnecting the top package to bottom package, and 0.4 mm pitch for interconnecting the bottom package to PWB. Using finer pitches for both packages allows the bottom package size to be reduced, decreasing the overall footprint on the PWB. The top memory package size may also be reduced, provided that the size of the memory devices does not prohibit further device shrinking. When µPILR contacts are used for package to PWB assembly, higher package stacking standoff is not needed. In mobile electronic devices where form factor is critical, it is desirable to reduce the profile of the component to achieve the lowest possible height. The µPILR contacts allow for a reduction in package to PWB standoff height compared with BGA interconnections, while still providing high reliability for mobile applications.

5. µPILR logic plus memory PoP test vehicle design.

µPILR reliability

We developed daisy chain test vehicles to evaluate package-to-board reliability performance of the µPILR interconnection. A set of four different test vehicles were constructed. The body size was 10 × 10 mm, and the full area of the package was populated with an array of µPILR contacts. The µPILR contact-to-contact pitch was evaluated in drop testing at 0.65, 0.5 and 0.4 mm pitches using 196, 324 and 529 total µPILR contacts, respectively. To simulate the mechanical properties of a functional device, a silicon die of 6.5 × 6.5 mm × 150 µm was attached to the top surface of the substrate. The component was then encapsulated with overmold to a height of 450 µm over the substrate.

Since this technology is targeted for implementation in high-volume manufacturing of mobile electronic assemblies, components were assembled to the test boards using standard SMT assembly processing equipment and techniques. SAC305 no-clean solder paste was screen-printed onto the PWB pads using 5-mil-thick stencils. The µPILR components were then placed using pick-and-place tooling and reflowed. No underfilling of the components is necessary. This is desirable, as it reduces cycle time and cost during the assembly operation.

Drop testing was performed to the specifications outlined in JEDEC standard JESD22-B111. The test board used non-solder-mask-defined pads with nominal metal pad size of 230 µm diameter for 0.4 mm pitch components and 260 µm diameter for 0.5 mm, and 0.65 mm pitch components. As specified, the component assembly on board was subjected to a half sine pulse of 0.5 msec duration and peak acceleration of 1500 gn.

Figure 6 shows drop testing results for the 0.4, 0.5 and 0.65 mm pitch test vehicles. For 0.4, 0.5 and 0.65 mm pitch components, first failures were recorded at 264, 340 and 426 drops, respectively. Additional test vehicles have been developed to analyze the performance of stacked homogenous PoP for high-density NAND and DRAM. Work is ongoing for these and other PoP configurations.

6. This Weibull plot shows drop test results for 0.4, 0.5 and 0.65 mm pitch test vehicles.

Conclusion

Package options for mobile electronics continue to evolve, incorporating increased functionality into smaller form factors. Applications must be evaluated carefully to determine which package options provide the best solutions for form, function and cost. New technologies are emerging that offer improved 3-D integration while taking advantage of existing infrastructure to control cost. This will undoubtedly help address the needs of future high-density mobile electronic devices.