Modeling, Simulation Gear Up to Meet Next-Generation Needs

Producing a working chip design has been getting increasingly complicated since the days of rubilith and Xacto knives. We live in an era in which circuit quantum effects complicate the lives of designers performing advanced work. EDA tool have come to the rescue, which provide the means to verify the increasingly complex chip designs, ensure that they will function as intended, and play “what if” games for the next technology node. Process technologies have also evolved well beyond the point from which a simple handoff was sufficient when a design was ready to be “siliconized.” Here, too, EDA has acted as both a lifesaver and a bridge to the future, which does not mean things have gotten better for those who provide it.

“Beyond 65 nm, basic design physics becomes worrisome,” stated Eric Filseth, corporate vice president in charge of DFM marketing at Cadence Design Systems (San Jose). “Subwavelength effects become severe, and systematic and random manufacturing optimizations and variability must be included in the equation with other optimization requirements through the design flow, such as area, power, timing, signal integrity and more. Design, implementation and analysis engineers must have the capability to model, simulate and optimize how a chip will yield, both from a functional standpoint and parametrically, and as early in the design flow as possible.”

“Electrical DFM has become crucial to determine whether something can be made, manufactured and if it’ll work,” said Carey Robertson, xRC/LVS product marketing manager at Mentor Graphics (Wilsonville, Ore.). “Several factors address the 'will-it-work’ proposition. One is whether there will be electrical failures. Working with increasingly smaller technologies, we’ve learned more about process nodes, etc., and electrical rule checking has become complex and obligatory. Before, we’d look at things like antenna failures; now we must do things like ESD checks and other electrical checking to identify catastrophic failures.”

Anantha Sethuraman, vice president for DFM solutions at Synopsys (Mountain View, Calif.) stated: “Variability must now be characterized. It breaks into three areas, the first being pattern definition variability, which comprises litho simulation, RET and mask data prep to understand exactly how it prints on the wafer. The second is structural, an understanding of device variability, to determine what shrinking thermal budgets do to device performance; looking at it in a small proximity area, like between two adjacent structures — layout-related or layout-induced stress variability. Contour-induced changes enhance this. The third is environmental — the actual physical location.”

From nuisance to problem

As the progression toward smaller nodes continues, troublesome areas once ignored are now critical, requiring modeling. For instance, chemical mechanical planarization (CMP) plays a bigger role because wire thickness has a greater effect on electrical performance at 45 and 32 nm than at 130 nm. Other processing effects, such as etch, stress, etc., must also be modeled.

“Below 130 nm, transistor leakage into the device substrate is a concern,” Filseth noted. “As with everything connected with smaller geometries, this varies. First, it was leakage concerns; now, it’s leakage variation, which can be an order of magnitude over the device’s operating conditions. Designers fret about manufacturability and electrical performance variations; third-order impact effects are becoming dominant.”

Over time, rules developed, such as not placing wires within a certain space of each other or avoiding some structures because they do not print well. Now, engineers are supplementing this with more detailed manufacturing process simulations, because solely using a set of rules with these problems forces designs to be conservative to cover each possible case at the cost of performance capability or reliance on empirical methods.

Sandeep Mehndiratta, product marketing director for custom ICs at Cadence, noted that modeling must deal with many physical effects, particularly when considering accuracy requirements for simulating these effects actively to represent things such as depletion, well proximity and stress effects, subthreshold region, etc. “Existing modeling standards are giving way to next-generation models, such as PSP and HISIM. These are currently being considered by the Compact Model Council [CMC] as industry standards to accurately model these once second- or third-order physical effects, resulting in silicon correlation and assimilation,” Mehndiratta said. BSIM4 is the standard CMOS transistor model, principally in 90 and 65 nm applications, and it is yielding to more accurate electrical effect modeling.

The trend is to represent these transistor electrical models — traditionally done in an equation mode — in a Verilog-A-type model to improve portability and complex equation representation. This refers to transistor-level physical effects, but electrical representations are also modeled (as is process data) to simulate the circuit performance with the correct electrical process representation. “The use of Verilog-A for compact device models poses a performance challenge for accurate simulation of the next-generation designs with analog, digital and RF domains represented on the same chip,” Mehndiratta said. “We provide simulation technologies to simulate design using these compact device models with the performance matching those of the native built-in equation-based models.”

Zhihong Liu, corporate vice president, R&D, simulation and modeling technology at Cadence, points out that a common feature of models being considered is that they are surface potential-based, making them more physically and specifically accurate in the weak subthreshold region. “Before, we dealt with the process region using the corner model approach with models representing different corners. This is inappropriate for fast nanometer structures-based designs. Designers now look to more accurate statistical analysis approaches to account for systemic variations, and apply Monte Carlo analysis to circuit design to get accurate yield and performance estimations,” he said. However, this further entangles the process, requiring more interim model extraction algorithms and complicating the mining of statistical information about the process iteration.

Another hurdle is that most of the complex modeling information at the design flow — the optical proximity correction (OPC) and layout-dependent data — is available only after the wafer has been laid out. The layout data is checked, put into layout-dependent models, and the circuit simulated. This flood of information and the models’ complexity challenge the simulator, slowing it and complicating design efficiency.

“There are several components to this,” Filseth said. “As we move beyond 65 nm and to 45, 32 and 22 nm geometries, what happens to printability? There are wires and transistors, yes, but what a designer initially draws will be different to how it actually appears in silicon. If we understand how manufacturing engineers will physically optimize these structures and account for this impact on transistor electrical behavior, this modeling becomes the bridge between manufacturing and design. ”

At 45 nm and beyond, the overall problem is the integration of multiple domains — RF, analog, baseband, custom digital — into a system that presents huge verification problems for integrators (Fig. 1 ). Verification and assimilation technologies of individual domains are mature, but as these cross-domains are brought together into a complete system, conditions — interfaces, interactions, loading effects, parasitics — change across all domains, complicating timely sign off with reliable verification of the whole system. “As designers move from architecture exploration to block-level development to RF design and to final full-chip verification, their simulation and modeling needs change too,” Mehndiratta said.

1. Cross-domain verification, forced by the integration of multiple domains into a single device, results in considerable verification difficulties, as interfaces, interactions, loading effects and parasitics change, complicate timely verification of the complete design. (Source: Cadence Design Systems)

Computer modeling time is now a design process schedule component. A major question is how to make manufacturing models as simple as possible, but no less simpler than they are now. An option is shifting from empirical methods to more physics-based ones — the math must reflect actual physics, relying less on vast amounts of data. The shift to statistical methods is another change. Silicon always varies a bit in manufacturing and, traditionally, this has been accounted for by testing at a range’s high and low ends and running two simulations per circuit, or one for each corner: one each for the fast and slow. However, there usually is more than just fast and slow. Thus, simulations were run a few times on different combinations of where it was thought variations would be and different points checked. To account for all variation axes at 45 and 32 nm, a large number of cases would have to be checked, causing designers to run into two serious problems: the simulation time required and the fact that with all those cases, the engineer must work at these three or all 13 possible worst-cases in the way the silicon comes back. This worst-case scenario forces a conservative design, resulting in performance penalties.

Designers want a more statistical or variation-aware model that shows what the mean silicon point, the mean performance, and the performance distribution are because it “knows” what the 1, 2 and 3σ points along all the various axes are, producing a statistical model of the device. Thus, doing these corners — or worst possible cases — becomes unnecessary, and the statistical model is more accurate. There may be a slight yield trade-off, but chip performance is improved.

“Consider an effect such as wire thickness,” Filseth said. “Whenever a metal layer is deposited, the wafer is planarized. But it’s never perfectly level; it has microscopic mountains and valleys. If two wires are close and one is thicker because CMP didn’t flatten it exactly the same way, it’ll conduct more electricity than its thinner counterpart, resulting in a timing difference. If this isn’t physically modeled, one sees variation between the two, which appears random unless modeled. If you mathematically calculate which geometries are thicker and which thinner, this is removed from the random variation equation, reducing the observed variation when going to a statistical method.” This is being done, learning empirically how much of the observed randomness, how much of that distribution, can be accounted for by factors that can be physically modeled to narrow the observed distribution.

Before, MOS transistor models such as BSIM3 and BSIM4 were sufficient. Now, one must look beyond those models into things such as gate depletion and transistor reliability. There is growing concern over transistor temperature instability issues, all of which complicate modeling. There is another snag: information overload, which challenges the simulator that uses circuit design information. As designs get larger and features shrink, the data is more intricate. An aspect of this is the interconnect parasitics introduced after the circuit is manufactured and laid out. Before, this information was unimportant. At 45 nm and below, it is critical because additional effects take place in circuit behavior and performance, and the simulator must handle them.

Making prediction accurate

Robertson indicated that more is learned about the physics around a device as it is laid out. “In determining how a MOSFET will perform, there are other effects ignored at larger process nodes. Additionally, when we take measurements off the ideal layout (typically ideal rectangles), we know they aren’t true to that we’ll see in silicon; these models are all parameter-driven. If we assume a particular W and L coming from a drawn layout and it’s radically different in the silicon, we won’t do a good performance predicting job. Device modelers accommodate this by biasing the model to account for optical printing issues, etc., but many biases are context-dependent.”

Mentor Graphics has integrated what it calls litho friendly design (LFD) in manufacturing prediction technologies to predict what contours will look like on a per-MOSFET basis. Instead of dealing with a global bias for how a transistor will change, a simulation is run and Ws and Ls are captured from this predictive contour. This is a silicon prediction based on the lithography tool’s dose and focus, showing what the MOSFETs will look like (Fig. 2 ).

2. EDA models must now make manufacturing prediction technologies part of their models to predict what contours will look like on a per-MOSFET basis. Such predictions are based on the dose and focus of the lithography platform. (Source: Mentor Graphics)

On the interconnect side, the issue is, again, accurately modeling the physical behavior to determine parasitic R and C value; however, since the silicon varies, accuracy is a concern, but so is binning the amount of variation into categories, best case, worst case, typical, etc.

According to Jim Falbo, an R&D engineer at Mentor Graphics, in traditional corner modeling, there is a separate rule set that runs extractions to produce net simulation models for each corner. “It’s an expensive process,” he said, “and the complexity of corners and the accuracy required has increased run time and engineering effort.” An approach called “sensitivity analysis” can be used, where there is a single rule file and a single extraction, allowing the engineer to generate multiple corners in a single run. This identifies how process variations alter parasitics. Thus, the designer (or simulation tool) can vary a physical parameter, such as metal thickness, width, spacing or dielectric constants, which would incur a change in the parasitic information. Ultimately, the designer would understand how that physical variation could translate into simulation differences. In a typical process corner, the difference between typical and RC worst may have a delta thickness variation of ~30%.

This allows an examination of lithography-induced variations when there is spacing-dependent variability. A drawn image can be taken, run through, determine what the actual image will look like on silicon and, using sensitivity parameters, get exact data of the actual silicon image as determined by LFD, and output the parasitics without re-extracting. This is much more efficient, as the extraction engine identifies how parasitics are dependent on these parameter variations and captures the model in the rule file.

A key piece to obtain accurate simulations is taking the variation’s three dimensions — the X, Y variation predicted by litho tools and CMP’s predicted Z variation — and integrating them into the device and interconnect defects (Fig. 3 ). This can be made into a structure to get interconnect parameters through a consistent system, providing a dependable silicon model. At the device level, designers have three device corners: min, typical, and max. For most interconnect corners, they do between five and seven, usually five parameters — typical, C best, C worst, RC best, and RC worst. If the engineer simulates across all process corners, s/he must do 3 × 5 or 15 simulations; this does not cover factors such as voltage and temperature corners. Now that optical contours across the device in the interconnect are available, the designer has a contour that predicts a corner. There is a correlation of the contour between what happens in the device and what happens in the interconnect.

3. Successful simulations use a variation’s three dimensions: the X, Y variation predicted by litho tools and CMP’s Z variation. These are then used to create a structure that can provide interconnect parameters consistently, resulting in a dependable silicon model. (Source: Mentor Graphics)

As designs grow in complexity and new materials are introduced, EDA providers must get closer to manufacturing to predict new process phenomena, so that the modeling mechanism simulates these and returns an accurate parametric number. Because processes are changing, it means more than just Rs and Cs are required. Variations, such as quantum effects, will require study at the device physics level. For proximity effects, designers need considerable physical information, particularly measurements to go into the model.

Sethuraman sees simulation reigning supreme as lithography gets increasingly difficult. “Simulation characterizes not only process components, but also things such as the illumination coming from the immersion — the resist, which is important in lithography simulations — and etch. All this must be characterized together. One could conceivably understand the performance or behavior of a device structure in a production environment by using actual populated production data.”

Modeling and simulation face hurdles in the requirement for better understanding of stress and proximity effects. It will be necessary to go down to the cell level to simulate and characterize these effects to understand how they affect transistor behavior in the entire cell and across the wafer. Taking stress information from the manufacturing side, abstracting it, and putting it in the design will be crucial.

As we move toward 32 nm and beyond, current design flows must improve to handle added intricacy and design efficiency. At 65 nm, there was concern over needing radical changes and having to discard everything being used. Some viewed 65 nm as too difficult and expensive, but the move to 65 nm took less time than it did to ramp to 90 nm. The shift to 45 nm may take even less. So 32 nm and beyond should be manageable as well.