Nanotechnology Brings New Memory, Solder, R&D Technologies
Paula Doe, SEMI, San Jose -- Semiconductor International, 7/18/2007
Nanotechnology innovations are enabling nanocrystalline flash memory, lower-temperature conductive inks and solder, and ways to make R&D more efficient, said speakers at the Nano Materials and Tools TechXPOT Tuesday morning at SEMICON West.
Nanocrystalline flash memory materials are qualified in multiple fabs and the memory technology is in evaluation with multiple flash manufacturers, who are targeting introduction at the 3x nm node, said Donald Barnetson, director of market development for memory at Nanosys (Palo Alto, Calif.).
With the skyscraper-like structures of NAND floating gate flash pushing the limits of scalability and charge trap flash technologies hard to erase with limited lifespan, Nanosys, and presumably its memory partners Intel (Santa Clara, Calif.) and Micron (Boise, Idaho), are looking at nanocrystalline memory instead. Other nanocrystalline approaches have typically deposited the crystals in situ, but faced problems with irregular particle size and distribution that impacted performance. Instead, Nanosys and its partners fabricate the metal nanocrystals separately, first adding a growth ligand to keep the particles in solution and then replacing that with another proprietary ligand to hold them a consistent distance apart. The solution of crystals is then spin-coated onto the wafer using conventional semiconductor industry track tools to create a uniform monolayer, limiting issues of dot-to-dot tunneling. Histeresis is ~14 V (7 V to program and 7 V to erase) — about the same as floating gate technologies, so it can extend existing architecture and potentially be integrated with fewer steps than either floating gate or charge gate technology. Barnetson also argued that reliable life will be 10 years, much longer than nitride alternatives, which have to use holes to erase the data.
Nanoparticles are also being used for printed applications, where smaller size brings lower-temperature melting or sintering to convert the inks to conductive traces. Silver circuits can now be made at temperatures down to <200°C with 30 nm particles, and can potentially be brought down to as low as 150°C, though the sintering process will take longer. With the current high cost of silver, however, much work is now focusing instead on copper and other potentially more economical printable conductive materials.
Nanotechnology may similarly be the solution to bringing down the temperatures for lead-free solder. Work with the Warm Manufacturing Initiative is using 5-10 nm particles of tin and tin-silver-copper to bring process temperatures down to 183°C of conventional tin-lead solder. “The first application will be for rework,” said Alan Rae, vice president of business development for NanoDynamics (Buffalo, N.Y.). The company and its partners have demonstrated workable soldering at these lower temperatures, though it still needs much reliability testing.
There are plenty of other problem areas where nanomaterials might deliver solutions to getting past the red brick walls on the current roadmap, said Mike Garner, Intel manager of external materials research and technology strategy, including line edge roughness (LER), next-generation interconnect, copper barrier cladding and interlevel dielectrics (ILDs), as well as the entirely new kinds of devices based on new physics that will drive the industry 20 years from now.
As early as several generations ago, self-assembly processes were found to impact LER, Garner noted. The problems turned out to be coming from high- and low-density regions in the resist that developed differently, caused by a self-assembly agent. Removing the agent solved the problem. But as dimensions approach 14 nm by 2020, careful submicron control of the resist structure will clearly be needed to get even 10% uniformity, which will be a sobering 1.4 nm.
The industry will also soon need nanoscale control of grain structure and sidewalls in interconnects, and perhaps new and lower resistance materials to replace copper, as reducing the grain size of copper produces more scattering and increases resistivity. The industry will also need precise control of the structure of diffusion barriers layers to prevent diffusion from the copper without making the barrier layer thicker than the copper. Interlevel low-k dielectrics could also still be improved by some new molecule that delivers the elusive higher mechanical integrity with low dielectric constant and low moisture absorption. All of these developments will also need better tools to characterize the composition and structure of all new nanoscale materials.
Other companies are proposing ways to make developing all of these new materials more efficient. Intermolecular (San Jose) aims to bring the semiconductor industry the systematic high-throughput research approach commonly used in the pharmaceutical industry, extended to polymer catalysis by Symyx (Santa Clara, Calif.). CTO Tony Chiang noted that typically the end user relies on separate optimization from different suppliers of the materials and process, and only hopes that combining them yields the optimal final solution. Instead, the combinatorial process does massively parallel initial deposition and characterization of separate spots of 500+ materials on one wafer, then can run and characterize the best candidates in 100+ processes at separate sites, and finally integrate and electrically test tens of separate sites with different process flows to correlate the materials and processes directly to electrical performance. The workflow for wet processing is most developed, but the company can also do physical vapor deposition (PVD) with masking shutters to isolate the separate sites, and said an atomic layer deposition (ALD) flow is coming next, with chemical vapor deposition (CVD) on the roadmap to come. Chiang noted that the fluid process is more sophisticated than just droplets, but also allows fluid flow and changes in boundary layers effects.
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| Tony Chiang, CTO, Intermolecular, discusses accelerating integration learning. |
Applications include a back-end-of-line (BEOL) copper clean currently in qualification at a leading foundry. With the PVD workflow, Intermolecular said it developed material and process for a new non-volatile memory (NVM) cell for a major supplier in 10 months, aimed at production late next year. The company is also developing a self-assembled molecular mask layer to allow cobalt capping, controlling leakage without post clean. The process did more than 11,000 experiments and 26,000 characterization sets in eight months, with three lots of wafers.
Meanwhile, Atomistix (Palo Alto, Calif.) said its modeling software can similarly shortcut the nanoscale research process by screening materials for the desired properties beforehand, taking into account quantum effects. And, unlike other such systems, it can do it not just for isolated systems but, with enough computer power, for entire devices. The software predicted that magnesium oxide would be a better insulator for MRAM than aluminum oxide, as turned out to be the case, and identified better passivation materials (gold or magnesium oxide) for the interface to separate the iron from the magnesium oxide to further improve performance. Other work found that missing carbon atoms in carbon nanotubes (CNTs), making five-sided rings instead of the usual six, did not reduce conductivity. “You can do cheap modeling experiments to screen materials and do real experiments only on the best ones,” said President Kurt Stokbro.
In other innovations to facilitate nanoscale research, Karma Technologies introduced a miniaturized module only a few inches long that contains both the detector and probe tip, so the whole unit can be changed out in ~20 sec, compared with the 10 min of tool downtime it might typically take to change and realign the tip in a conventional probe microscope. The used modules are refilled and realigned offline, using the company’s tooling to increase speed.
Energetiq (Woburn, Mass.) is providing researchers and nanomaterials developers with short-wavelength light that provides high energy without heating or electrical charge damage for cleaning or resist development. The company produces the light without using electrodes, which it says produces the necessary high temperatures without the usual problems of contaminating surfaces that shorten source life. Instead, it uses inductive or magnetic coupling to put in high amounts of energy for high output light. CEO Paul Blackborow said the deep ultraviolet (DUV) source provides at least 500 mW/cm2 of 250-400 nm light at the wafer surface, with ±5% uniformity.
