Transcript: Test Must Keep Pace With Consumer Devices

Chetan Desai, vice president and general manager of ATE products for Credence, discusses design for test (DFT) and other significant test trends.

Laura Peters, Lead Technical Editor -- Semiconductor International, 6/30/2007

Listen to the audio intervew
 
Peters: Hi, this is Laura Peters, lead technical editor with Semiconductor International magazine, and today I’m interviewing Chetan Desai, vice president and general manager of ATE products at Credence. We are going to talk about some of the trends that he’s seeing in preparation for SEMICON West next week.
 
Desai: Hi, Laura. Nice to chat with you, and thank you for the opportunity.
 
Peters: Thank you. First, in the broad areas of wafer sort and final test, what are the most significant developments that you see taking place in the market?
 
Desai: If I classify the two areas, because they have distinct challenges and inflections emerging between wafer sort and final test, I’ll first comment on wafer sort. In general, we’re seeing a significant move toward known good die [KGD] test methodologies for logic and mixed-signal devices. This has traditionally only been applicable to memory devices, but the economics of system-in-package [SiP] are demanding that our customers figure out a solution for better test coverage at wafer sort for SoC [system-on-chip] applications, so KGD for SoC is going to be an interesting development that is ongoing now.
 
We’re also seeing some additional focus, because of the availability of denser probe technologies, wafer-level CSP [chip-scale packaging], for higher levels of parallel testing in the wafer sort arena. And, while thermal management remains a challenge for some of the high-power devices at wafer sort, increased multisite test is definitely evolving very rapidly in wafer sort. The other part is our customers are attempting to move more and more functional coverage into wafer sorting compared to typical final testing. This is largely driven by their desires to optimize their production flow and find defects earlier in the verification cycle.

These are the three key trends I see in wafer sort. If I switch over to final test, clearly across the spectrum of devices from the very low-end linear discrete market all the way to the high-end SoC, there’s an increasing focus on parallel test. The magnitude of parallelism during test is increasing across the board – a lot of it enabled by some material handling innovations that are coming into the marketplace. Besides the material handling steps, the packaging innovation, especially around SiP, with package-on-package or stacked die solutions for SoC, are driving the need for ATE platforms that have very broad functionality. Most of our customers have effectively sidestepped the hurdles of single die or single process integration for these functions and have moved towards SiP as an easier answer for their functional integration. This is demanding some changes and evolution in the ATE solutions that are being provided to these markets.

The last very important trend we see is that the ASP [average selling price] erosion on our customers’ devices, especially in the high-performance segment, is actually accelerating. We are finding, in the consumer wireless arena, the increasing functional integration is actually stabilizing the ASP and actually potentially increasing it a little bit. On the high-performance side, ASP erosion is driving dramatic innovation for lowering the cost of test. That requires very heavy partnerships between our customers, us as an ATE supplier and EDA vendors. That cooperation has probably the most significant possibility of breakthrough in cost of test.

Peters: When you talk about SiP becoming a more significant trend for your customers, how quickly do you see that happening? Obviously, it depends on the format – in some cases, they are using package-on-package; in other cases, there’s even tighter integration. How quickly is the industry going to these more integrated package and die-to-die connection methods?

Desai: That’s a good question. Clearly, for the mobile handset market – anything that is handheld for the consumer – this trend is already there now. We are seeing a lot of packaging innovation coming to bear on the cellular handset market and PDAs. Because of the form factor demands for that market in terms of shrinking size and then time to market also for those customers, because it turns out these different functions have distinctly separate and asynchronous innovation cycles. So people are putting the digital baseband with the RF piece together, the RF standards are evolving at a certain cycle and pace in the market, so those devices operate or go to the next generation completely asynchronously to the rest of the multimedia functions in that SiP. So that process of having a SiP solution work as a single die offers these customers the ability to keep morphing the function as each of the individual parts evolve. So, for the handset market, which is a huge growth area for the consumer market, this is already the case. It’s very well-established.

Peters: You referred to more design for test coming into play for system-on-a-chip, and obviously that can have RF components and logic and memory and so forth. To what extent are DFT methods being incorporated today?

Desai: My assessment is that in the digital and memory domain, DFT is very prevalent. Most of the embedded memory blocks are largely BISTed today within these devices. Logic based on DFT is very widespread. The new challenge in the digital domain for DFT is really in the area of the jitter tolerance and assuring the I/O driver integrity as the bus speeds on these devices are growing. So, in the past, and to a great extent today, the device and its DFT has largely been focused on generating the test data and providing a loop-back path, and they are relying on the tester or the ATE equipment to provide the rest of the capability for jitter injection/jitter tolerance on assurance for quality, and those domains. DFT is going to evolve to tackle these challenges of high-speed buses.

Analog DFT is still not a very mainstream activity. Most of our customers still perform full functional test on their analog or mixed-signal cells. So this is still in its infancy.

The other area where we are seeing significant focus on is around on-chip scan data compression/decompression. This provides significant test time and cost benefits to our customers. It also simplifies ATE memory architectures. So on-chip data compression/decompression is clearly a trend that will continue.

Peters: Chetan, I’d like to thank you for joining me, and hope you have a great week. This is Laura Peters and I’ve been speaking with Chetan Desai, the vice president and general manager of ATE products at Credence.

Desai: Thank you very much, Laura.

Peters: Thank you.