Air Gaps: Much Ado About Nothing
Peter Singer, Editor-in-Chief -- Semiconductor International, 7/1/2007
"With the theoretical minimum of k=1, air is the ultimate low-k material, which makes air gaps the dream of any interconnect researcher. But whether they will become a dream or a nightmare will depend on their behavior and reliability in real-life applications." This quote, taken from IMEC's (Leuven, Belgium) Ludo Deferm, appeared in the March 2005 issue of Semiconductor International and accurately captures that air-gap status quo.
In the past two months, the air-gap debate has taken center stage, as IBM (East Fishkill, N.Y.) announced in early May that it had made a breakthrough in fabricating chips with air gaps , showing a 35% increase in signal speed with 15% less power consumption, compared with conventional technology. "Air gaps" are something of a misnomer, as the gaps are actually a vacuum that is absent of air. Plain air, of course, contains moisture, which would cause corrosion and degradation of surrounding copper lines.
In a keynote at the Microprocessor Forum held later in May, Mark Bohr, Intel (Santa Clara, Calif.) senior fellow and director of process architecture and integration, dismissed air-gap technology, saying: "The cost and the reliability issues with interconnects are very important, and I don't think that air gaps are the solution to those. We are pursuing lower-k versions of existing dielectrics — I think this is more promising than air-gap technologies," he concluded.
At the International Interconnect Technology Conference (IITC) last month, the pros and cons of air-gap technology were a focal point of discussion. IBM's Dan Edelstein, IBM Fellow and chief scientist of the air-gap project, addressed Bohr's comments at an Applied Materials (Santa Clara, Calif.)-sponsored panel session, saying the associated costs were not as high as one might assume, because it would only be used on the most critical layers. Also, while early announcements emphasized a "self-assembly" approach, air gaps can also be fabricated using two simple and inexpensive masking layers.
Air gaps for interconnects and a similar technology for fabricating transistors with minimal parasitic capacitances called "Silicon on Nothing (SoN) " have been the subject of investigation for at least six years, but IBM's announcement that it was moving air gaps into production indicates remarkable progress — more than what has so far been demonstrated. IBM said the self-assembly process has already been integrated with the company's state-of-the-art manufacturing line in East Fishkill, N.Y., and is expected to be fully incorporated in IBM's manufacturing lines to be used in chips in 2009. These chips will be used in IBM's server product lines and thereafter for the chips that IBM builds for other companies.
IBM likens the "self-assembly" process to the natural pattern-creating process that forms seashells, snowflakes and enamel on teeth, enabling the nanoscale patterning required to form the gaps. "This is the first time anyone has proven the ability to synthesize mass quantities of these self-assembled polymers and integrate them into an existing manufacturing process with great yield results," Edelstein said. "By moving self-assembly from the lab to the fab, we are able to make chips that are smaller, faster and consume less power than existing materials and design architectures allow."
This patented process provides the right environment for the compounds to assemble in a directed manner, creating trillions of uniform 20 nm holes across an entire 300 mm wafer. Once the holes are formed, the carbon silicate glass is removed, creating a vacuum between the wires.
In an interview with our sister publication Electronic News, Bernie Meyerson, vice president and chief technologist of IBM's Systems and Technology Group, explained the process in this way: "Air gap works. It has been used to build real microprocessors, not a little demo chip. The funny thing about it is this is not based on trying to define things lithographically, which is the most expensive imaginable way to build a chip. It is actually based on nanotechnology, or more specifically, self-assembly. Self-assembly is not well understood, and many [including Intel] have no expertise in this area. It is based on materials segregation. We invented a polymer, and if you heat it up modestly, what happens is it segregates into two different materials that are chemically different. The material that segregates out of the polymer forms very uniform nodules, about 100 atoms across. These nodules are of a different chemical composition than the matrix that's left behind. These nodules repel each other, so you have this perfectly symmetrical array of them. You use an etchant that selectively etches out just the nodules to create the world's finest Swiss cheese."
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