3-D TSV Chips Take Off

After more than a decade of researching 3-D chip stacking at its T.J. Watson Research Center and other labs around the world, IBM (Armonk, N.Y.) is now running chips using through-silicon vias (TSVs), also known as through-vias, in its manufacturing line. "Big Blue" plans to make sample chips available to customers later this year, and is hoping to enter production with products using TSV technology in 2008.

IBM's move to TSVs is a significant one in that it enables the jump from 2-D chip layouts to 3-D chip stacks — taking chips and memory devices that traditionally sit side by side on a wafer and stacking them on top of one another. The resulting component "sandwich" reduces the overall chip package size and increases the speed of data flow among the various functions of the chip.

How do TSVs work? "The nature of a TSV is essentially the same as a contact hole," said Wilfried Haensch, senior manager of IBM's research division. "The only difference is that you have to drill a really deep hole vertically through the silicon material itself for TSVs, which requires a special etch process [Figure ]. Then you can do a tungsten or copper fill, depending upon the application of the chip."

This thinned wafer is ready for bonding to another wafer, where a through-silicon via (TSV) process will connect the wafers together by etching thousands of holes through each layer and filling them with metal to create 3-D integrated stacked chips. (Source: IBM)

What are the advantages of 3-D TSV technology over other technologies? There are many when compared with alternative technologies, such as system-in-a-package (SiP) and system-on-a chip (SoC), according to Sematech (Austin, Texas). For example, TSVs offer greater density in the same footprint, as well as improved functionality, higher performance, lower power consumption, lower cost, greater manufacturing flexibility and faster time to market.

How will TSVs change advanced packaging? Compared with 2-D chips, 3-D TSV chips conveniently eliminate the need for wire bonding and reduce the distance information on a chip needs to travel by a whopping 1000×. They also allow the addition of 100× more channels or pathways for that information to flow.

"From a purely packaging standpoint, the most significant way TSVs will change advanced packaging is that they will allow you to eliminate wire bonding for certain applications," Haensch explained. "In our first application of the technology, which is a wireless communications chip that will go into power amplifiers for wireless LAN and cellular applications, we replaced wire bonding with TSV technology."

Their first product using TSV technology, an RF chip, increases the power efficiency by ~40%, compared with conventional wire bonding, according to Haensch. "This is a number that you can apply only to this application. The power efficiency number will vary by application," he said.

IBM is hoping to be the first to market with products using 3-D TSV technology, and feels that the time is right. "TSV technology is a key element for advanced packaging, and we feel comfortable that we can meet reliability concerns with this technology," Haensch said. "As you can imagine, there are lots of things we had to think through. It's one thing to do an experimental stage in the lab, but yet another to actually bring it onto the market."

And IBM's not alone in moving forward with TSVs. Samsung (Seoul, South Korea), Tessera (San Jose), Intel (Santa Clara, Calif.), Elpida (Tokyo), IMEC (Leuven, Belgium), Sematech and many others are exploring or using TSV technology.

In fact, Sematech announced earlier this year that its 3-D Interconnect Initiative is working on a roadmap, due out by the end of the year, that will provide details about research into 3-D technology options (including TSVs), unit processes and metrology, and will ultimately demonstrate 3-D's functionality and reliability.

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