3-D CMOS Imager Uses SOI

The performance of 3-D ICs was analyzed and predicted years before the chips themselves could ever be fabricated.^1,2 The analyses assumed vertically stacked ICs with dense 3-D vias for electrical interconnection, and predicted reductions in power dissipation, signal latency and noise of such digital 3-D ICs and increased quantum efficiency from 3-D imaging circuits. While true 3-D chips have not been available, some of their advantages have been approached through chip-stacking techniques.^3,4 These techniques utilize packaging technologies that exploit the vertical dimension through the attachment of chips to carriers and other chips using a variety of bump bonding or other interconnection techniques. Today, 3-D technologies are being globally developed to achieve those performance goals.^5–7 Lincoln Laboratory's (LL) approach⁸ is one of wafer-scale 3-D integration technology and design methodology. The building blocks of this 3-D circuit integration technology are fully depleted silicon on insulator (SOI) circuit fabrication,⁹ precision wafer-to-wafer alignment, low-temperature wafer-to-wafer oxide bonding, and electrical connection of the circuit structures with dense 3-D vias.

As part of a 3-D Multiproject program, 3-D design rules have been developed, a design kit has been published, and modifications have been made to computer-aided design (CAD) tools implemented to support 3-D circuit design and fabrication.

The 3-D chip and assembly process are illustrated in Figure 1 , where each functional section of a 3-D IC is labeled a tier and consists of the interconnect and active silicon. Tier 2 is transferred to the base tier, Tier 1, after face-to-face infrared (IR) alignment and oxide-to-oxide bonding at 275°C. The handle silicon of a

1. Wafers with circuits are planarized, aligned, and bonded face to face (a); the handle silicon is removed (b); 3-D vias are etched through the deposited buried oxide (BOX) and the field oxides (c); tungsten plugs are formed (d); and after Tier 3 is transferred, bond pads are etched through the BOX for testing and packaging (e).

We show the 3-D chip after bond pads are etched to expose the back of the first-level metal for probing and wire bonding. If the 3-D chip is a digital circuit, the bond pads are etched through the BOX and deposited oxides of Tier 3. If it is a backside-illuminated imager, Tier 1 is a bulk silicon detector wafer in which photodiodes were fabricated. An additional transfer to a carrier wafer is then required, and bond pads are etched after thinning the backside of the detector wafer to tune the silicon to the required optical absorption. The cross-sectional scanning electron micrograph (SEM) of a three-tier ring oscillator (Fig. 2 ) illustrates interconnections between tiers and the compactness possible with the 3-D technology.

The 3-D via pitch is a critical factor of the 3-D technology, and is dependent on:

• The design rule that the 3-D vias be fully landed
• The wafer-to-wafer alignment tolerance
• The oxide-etch aspect ratio of the vertical vias

A precision wafer-to-wafer alignment system with an overlay goal of ±0.25 µm was built in-house to decrease the pitch of 3-D vias. The system (Fig. 3 ) includes IR alignment system; a six-axis piezoelectric stage with nanometer-scale resolution to provide X, Y, Z, T, tilt and tip motions; and a precision XY air-bearing stage controlled by an environmentally compensated laser interferometer to map the grid distortion of wafers before alignment. The system has achieved 3σ overlay repeatability of <0.4 µm. Overlay of ±0.25 µm will require wafer mapping before 3-D integration to bond wafers with equivalent grid distortion.

2. A cross-sectional SEM of a three-tier 3-D IC with 10 levels of metal. The tiers are bonded and interconnected with tungsten plugs; the conventional interlevel connections are seen in the fully depleted silicon on insulator (SOI) tiers. Note that the 3-D vias are located in the isolation (field) region between transistors. The tungsten plug connects the annulus to the 3-D land (inset).

The wafer-to-wafer bonding process in 3-D integration must prevent wafer slippage between wafer alignment and wafer bonding, and the bond must be sufficiently strong to withstand the 3-D fabrication process. Wafers to be bonded are coated with 1500 nm of a low-temperature oxide, and 1000 nm of the oxide is removed by chemical mechanical planarization (CMP) to planarize and smooth the surfaces to a roughness of <0.4 nm root-mean-square. The wafer surfaces are activated by hydrogen peroxide to acquire a high density of hydroxyl groups. The wafers are then aligned and bonded. When the surfaces are brought into contact, weak (~0.45 eV) hydrogen bonds are created at the interface, which allow the wafer pair to be removed from the aligner without disrupting the bond and wafer alignment. The bond strength is increased by a 275°C anneal that creates a surface energy of ~1000 mJ/m², which is sufficient to allow removal of the handle substrate and subsequent 3-D via processing without disturbing the aligned pair.

3. The precision aligner designed to achieve submicron wafer-to-wafer overlay.

The 3-D via (Fig. 2 , inset) consists of a metal annulus in the upper tier, a metal land in the lower tier, and a tungsten plug that electrically connects the two features. The plug is formed in an oxide-via hole. After etching, tungsten is deposited and planarized by CMP. The oxide 3-D via etch was developed in a cluster tool from Trikon Technologies (Newport, South Wales, UK), where etch conditions were determined by balancing polymer deposition (used to achieve a vertical sidewall) and wafer bias (to sputter the deposited polymer from the base of the via during etching). The yield of a 10,000 3-D via chain increased from 35% to 100% by using a chlorine-based gas to etch the edge of the annulus and adding a small amount of oxygen to the oxide etch to remove the residual etch polymer. The current process results in a 3-D via with a median resistance of 0.75 Ω.

In 3-D technology, variations between wafers in X-Y die placement and rotation add to the overlay error of the 3-D via; the error is doubled if one tier is flipped with respect to the other. To minimize the overlay error, the first level stepped on each wafer must place the center of the exposed die pattern coincident to the wafer's center to within 100 µm, and each die must also be parallel to the wafer flat to within 5 ppm to meet the alignment budget. Tier distortion that occurs during 2-D and 3-D fabrication degrades the registration between two tiers so that 3-D vias may not be fully landed and it must be controlled. Wafer bow was a major source of tier distortion. We were able to minimize bow by depositing stress-compensation oxides on the backsides of the wafers before wafer-to-wafer alignment.

4. The 3-D Multiproject chip includes contributions from 21 institutions, MIT-generated circuits and numerous test structures to characterize 3-D design issues.

The "low-hanging fruit" of 3-D technology is focal plane design and fabrication, because the imaging tier has a 100% fill factor, and the analog and digital processing tiers are below the imaging tier. Using the 3-D technology discussed above, we were successful in the design, fabrication and operation of avalanche photodiode (APD) imagers and 3-D visible imagers. The 3-D chip¹⁰ is a 64 × 64 bit laser radar (LADAR) imager with 50-µm pixel spacing composed of Geiger-mode APDs in Tier 1 that are biased at 25 V and two high-speed, all-digital CMOS timing circuits in Tiers 2 and 3 that operate at 3.3 and 1.5 V, respectively.

The 3-D LADAR circuits achieved a 0.5 nsec timing quantization, representing the first functional three-tier circuits with active circuits and devices on all tiers. It is also the first demonstration of three different process technologies integrated into one 3-D chip.

A two-tier 1024 × 1024 visible imager with 8-µm pixels was also demonstrated,¹¹ where Tier 1 is a p+n photodiode and Tier 2 is a fully depleted SOI tier operated at 3.3 V. This is the densest 3-D imager circuit developed using this 3-D technology, and illustrates the realization of a 100% imager fill factor by 3-D integration. The high degree of pixel functionality (Fig. 5a) is an image acquired by projecting a 35 mm slide onto the CMOS circuit side of the 3-D integrated imager. Each pixel of the 1024 × 1024 array includes a reverse-biased p+n diode (in Tier 1), a reset transistor, a source-follower transistor, and a select transistor in Tier 2 (Fig. 5b ). Measured pixel operability is in excess of 99.9%, and the principal yield detractor was column or row dropouts, not defective 3-D vias.

5. Output from a 1024 × 1024 imager with an 8 µm pixel and 100% fill factor (a). The image was acquired by projecting a 35 mm slide onto the CMOS circuit side of the 3-D imager. The pixel circuit is in Tier 2, the 3.3 V fully depleted SOI tier. The photodiode is in Tier 1 (b).

Heterogeneous integration

The feasibility of heterogeneous integration of dissimilar materials while building 3-D IR focal planes was recently demonstrated. Six-inch indium-phosphide wafers were bonded to oxidized silicon substrates,¹² and high-yield 3-D via chains were fabricated to show the applicability of the 3-D technology to materials other than silicon. This is a major step toward the integration of mixed materials in 3-D ICs for digital and imaging applications.

Two- and three-tier digital and imaging 3-D ICs with a wide range of applications were demonstrated using the 3-D SOI technology. Results from this program suggest that:

• 3-D SRAM memories will have higher bandwidth performance caused by reduced interconnect delay.
• 3-D field-programmable gate arrays (FPGAs) will offer greater design and flexibility in programming.
• 3-D interconnect tiers will provide reduced signal delay and latency and better RF isolation between and within tiers.
• MEMS will be integrated into 3-D structures.

In other words, the long wait is over; 3-D is here!

This work includes contributions from the entire 3-D Circuit Technology group at MIT's Lincoln Laboratory, including Brian Aull, Chenson Chen, Chang-Lee Chen, Craig Keast, Jeffery Knecht, Vyshnavi Suntharalingam, Brian Tyrrell, Peter Wyatt and Donna Yost. The 3-D Multiproject Program is funded by the Defense Advanced Research Projects Agency (DARPA) under Air Force contract #FA8721-05-C-0002. Opinions, interpretations, conclusions and recommendations are those of the authors, and are not necessarily endorsed by the United States Government.