Atomic Layer Control Gives Better Performing Gate Materials, Uniform Batch ALD
Paula Doe, SEMI, San Jose -- Semiconductor International, 6/29/2007
Some of the most interesting developments in wafer processing technology continue to involve more sophisticated atomic level control, from cutting gate leakage with epitaxial monolayers of silicon to getting more uniform large-batch deposition of thin films.
MEARS Technologies (Waltham, Mass.) is now down to fine-tuning its manufacturing process and working on licensing terms with specific partners for its technology to increase drive current and decrease gate leakage. Gate leakage is decreased by modifying the silicon lattice vertically, much as strain modifies it horizontally, to increase current flow horizontally while decreasing it vertically. Company CEO Steve Levy noted that the company has spent a lot of time protecting the process, so a customer who licenses the IP can tweak it to use as needed to fit into a production flow. The actual product remains at least 12 months away for integration into the flow.
The company also suggests that a conformal film of the directionally conductive silicon could be wrapped around the fins or other shapes that might be used on non-planar 32 nm devices, where it will be hard to use strained silicon. “I think what scared people off of 3-D so far is the problem of how to maintain the gains of strained silicon if they go 3-D,” Levy said.
President and CTO Robert Mears said that he started the company with an idea for some fairly simple changes that could improve a material’s electrical properties. “In the course of refining the idea, we found that it worked particularly well to make silicon more efficient by increasing conduction in the horizontal direction and impairing it in the vertical direction,” he said. “Then we realized that it could be done with an epi step on a standard epi tool with subtle changes to the recipe to give the material an inherently 2-D nature.” Over the past 4-5 years, the company has grown these single atomic layers of silicon on more than 1000 wafers with its own epi tools, and runs many device wafers through testing at ATDF and customers sites on their wafers. He reported a 60-80% reduction in gate leakage over strained silicon.
Mears said that the manufacturing cost will be less than strain, and the process meets customers’ throughput guidelines for inserting this channel replacement layer of epitaxial silicon. “We do slow the epi process down to get better control, but then we’re only making a very thin 100 A layer,” he noted.
Levy said their tests have shown that the technology can be used along with strain, silicon on insulator (SOI) and high-k/metal gates to complementary effect. Although most initial interest is for high-performance 45 nm devices, Levy noted that it also has the potential for lower-power 65 nm applications as well.
Aviza Technology (Scotts Valley, Calif.) said that its Verano 5500 variable batch atomic layer deposition (ALD) tool is showing uniform results with various films on each of up to 100 wafers. “We have full load data from the top, middle and bottom, and the results are the same, whether it’s 5 or 100 wafers,” said Subrata Chatterji, vice president and general manager of Aviza’s ALD business unit. The tool uses individual injection and exhaust for each wafer and an across-flow technology to distribute the gas across the wafer to create what Aviza says is a uniform, single-wafer-like environment for each wafer in the batch. The tool’s small reactor volume enables an efficient use of chemicals.
Memory makers using high-k dielectric capacitor films are driving the demand for ALD tools, and their high-wafer volumes create low cost of ownership (CoO) advantages found in batch tools, which Chatterji said can now match single wafer on specs for Al2O3, HfO2, HfSiO2 and ZrO2 with economical throughput. “Almost every customer wants variable batch for improved CoO and higher productivity. Now people are looking to transition over,” he said. He figures batch tools may make up 40-50% of the ALD market now by units, because the big DRAM makers buy in volume, while R&D labs are still among the main buyers of single wafer tools.
But extending batch process to next-generation materials gets more complex, as the hafnium and zirconium precursors have lower vapor pressure, which makes them harder to inject into the chamber and the high-aspect-ratio wafer features, and requires a direct liquid injection unit and vaporizer to generate enough chemical vapor to provide large-batch uniformity and step coverage. Single wafer may still offer better control of these materials, but across-flow technology could have the edge in getting control with production level throughput, according to Aviza. “Logic makers using high-k materials like HfSiO2 are showing some cautious interest in standalone batch processes as well,” Chatterji said, “though there’s no consensus yet if they can afford to break the vacuum between steps now done in sequential processing in one chamber with single-wafer tools.”
And single-wafer throughput will remain manageable for very thin films. “Up to 80 angstroms, single wafer is fast enough,” Chatterji said. “There will be a substantial market for both approaches.”
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