SEMICON West 2007 Executive Outlook
Industry executives expect to see increased emphasis on energy conservation, both with tool efficiency and in fab operations, and, on a broader scale, in the development of processes for solar cell fabrication. At the device level, leading-edge 45 nm logic devices are beginning to incorporate high-k dielectrics and metal gates, while the big news in the back end has to do with chip-to-chip integration using through-silicon vias (TSVs), package-on-package (PoP) and other small form-factor approaches.
By Staff -- Semiconductor International, 6/15/2007
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In 2006, the industry had a difficult time introducing 45 nm CMOS technology into the development stage, dealing with increasingly complex issues such as gate integrity and process variability at such small dimensions. As a result, it is expected that the 45 nm technology will not be introduced into volume production before the end of this year. At the same time, research today is focused on 32 nm and below CMOS processes, continuing to follow the well known aggressive scaling path of Moore’s Law.
Meanwhile, existing “older” technology nodes used in manufacturing today may get a second life. These technology nodes, such as 180 or 130 nm CMOS, show the promise of a whole new industry driver. This is because these technologies are sufficiently scaled down so that they can be used to develop smart devices and systems, such as integrated smart sensors, power devices, CMOS MEMS devices, bio-chips, and so on.
Whereas process scaling R&D is mainly driven by memory requirements, processor and advanced logic applications, such smart devices can be developed using a 130 nm CMOS baseline process integrated with sensor and actuator functions, or processes with optimized specifications for power-handling capacity, operation voltages and drive currents. It will be critical to combine an increasingly larger set of expertises, ranging from CMOS process and design technology development over packaging and interconnect technologies to bio-nano domains.
We believe the industry will see an increasing drive from this so-called “More-than-Moore” route next to the continued aggressive scaling represented by Moore’s Law. One could wonder what this will do with the progression of consolidation in wafer fabs and the shift toward a fabless foundry model. It might give rise to a whole new revival in semiconductor manufacturing.
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IC manufacturers continue to aggressively pursue design rule shrinks driven by the benefits of reduced die cost and increased IC functionality. NAND flash devices lead the roadmap in shrink rate and timing because of both market forces and the scalability of the lithography for these devices. Scaling of DRAM and logic devices is more difficult due to the nature of the patterns of these devices and the relationship to other lithography parameters, such as overlay and CD uniformity.
Lithography continues to be the main driver of shrink, with current resolutions down to below 40 nm half-pitch. This is achieved by using the latest-generation 193 nm-based water immersion systems with a numerical aperture (NA) of 1.35 in combination with resolution enhancement techniques (RETs), such as phase-shift masks and polarized strong off-axis illumination.
To increase the NA beyond ~1.35 using high-index fluids and glasses is challenged by the need to mature new optical materials and immersion fluids. Furthermore, such high-index immersion has limited extendibility, and would arrive too late for leading device manufacturers.
The extension of 193 exposure wavelength (ArF) with double-patterning techniques to reduce k1 below 0.25 is expected to be the only technology available for volume manufacturing at sub-40 nm resolution in the 2008-2009 timeframe. Double patterning is likely to be used for the highly repetitive patterns of NAND flash devices, but may prove more difficult for the complex patterns encountered with DRAM and logic devices. These more extensive lithography processes also require tighter tolerances for overlay and chemical dispense units (CDUs), which also affect the scaling efficiency.
In the long term, wavelength reduction with extreme ultraviolet (EUV) remains the preferred technology for volume manufacturing of devices beyond 32 nm. The increased process complexity, lithography performance requirements and cycle time with double patterning make EUV a potential cost, performance and cycle time improvement opportunity for IC manufacturers, which is driving broad collaboration to mature the source, mask and resist infrastructure for this optical lithography technology.
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Extending the semiconductor roadmap using optical lithography is the clear message we have seen from the scientific community in the past two years. At least the next 3-4 technology nodes down to λ/6 or even λ/8 will be supported by sophisticated resolution enhancement. This will include highly accurate and distributable models describing the full vertical flow from tape-out through mask patterning and etch all the way to wafer imaging, including double patterning, again etch and even chemical mechanical planarization (CMP) — a virtual fab based on patterning synthesis.
The disaggregation of design, tape-out, mask and eventually wafer fab over the past 20 years is now a thing of the past. The deep-subwavelength regime of the 65 and 45 nm node has led to a much higher level of integration of design for manufacturing (DFM) into technology and yield ramp of new processes and products. But we face new challenges in double patterning technology (DPT), including advanced patterning films and the modeling of these new technologies all the way through etch — on multiple film stacks. We also need to factor in a budget buffer for overlay. Cell libraries on the design side need to follow very restrictive design rules to accommodate the coloring challenges of DPT. These patterns need to be decomposed into two or more separate mask layers, and the models in resolution enhancement techniques (RETs) need to synthesize these levels with a clear understanding of the interdependencies and interactions between the various patterning steps and topologies.
At this year’s SEMICON West, we’ll see emerging methodologies that answer these challenges through hardware and sophisticated modeling software. Hand-in-hand, they will form a virtual fab environment, allowing design engineers on one side to adjust layouts for requirements in lithography, and on the other side working with the specifics of the tools and process, including chemical vapor deposition (CVD), lithography, etch and CMP, and feeding downward information needed for metrology and inspection. Every nanometer and every yield point is a new battle — we can only win if we are in it together.
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For many years, the semiconductor industry has followed Moore’s Law (no relation, unfortunately) by producing smaller and smaller 2-D structures. Now, we are seeing a significant shift in the semiconductor industry from what were 2-D geometries for both devices and packaging to 3-D geometries. These 3-D structures allow the designer to get more function from a smaller area by taking advantage of the 3-D either through the substrate (e.g., through-wafer via), into the substrate (e.g., capacitors in deep-trench DRAM) or above the substrate (e.g., finFETs). This major shift affects everything from design and process tools through metrology tools and packaging. In particular, although it has been talked about for many years, we believe the time for 3-D IC structures has come, and will be a major theme at SEMICON West.
The change from planar (2-D) geometric thinking to 3-D geometry has lead to new challenges in the development of process control tools to produce these structures and metrology tools (and technologies) to create the data needed for advanced process control. To successfully use these tools, process engineers, designers and managers need to expand their understanding of process, design, measurement and control to effectively use the expanded data provided and improve yields. All of this is being done while the window for time to market is shrinking.
New dimensions, new structures, new technologies and a new way of thinking should make for a most interesting SEMICON West.
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Key themes at SEMICON West will be innovation and emerging technologies, particularly for the back end/packaging and photovoltaic (PV) markets.
With consumer demand for smaller, more functional devices now affecting nearly every aspect of IC manufacture, the packaging sector is no different at 45 nm and below. Shrinkage continues to play a role in driving the need for thinner wafers for stacked die, among other key technology advances heating up the spotlight on the back end. We are now focusing more heavily on establishing new industry partnerships to accelerate innovation, and we expect this trend is true for the entire industry — not only to reduce cost of manufacturing per unit, but also to do it better, smaller AND faster. Whether its logic, memory or MEMS packaging, improvement in thin wafer/die handling, working with new materials, and thermal management are just a few of the variables forcing the industry to innovate and adapt. In the back-end sector specifically, traditional dicing technologies are reaching their limits — whether it be cost, performance or yield issues for 45 nm and below manufacturing — there will be an accelerated need over the next few years for new laser solutions.
Another key topic for discussion at SEMICON West will be the PV market and the issues surrounding challenges with manufacturing and the viability of solar cells as an alternative energy source. It is certainly a hot topic in Europe at the moment, with much of the innovation in this field stemming out of this part of the world. While the challenges here are as great as the market potential, we expect SEMICON West will be another important platform to discuss how semiconductor OEMs can apply their technology and expertise in the PV manufacturing market in light of the many synergies offered between the two vertical markets. Also, similar to the way OEMs have thrived by successfully enabling continued advances in the semiconductor industry, there are vast opportunities to do the same in the PV market, particularly as imminent high-capital investment decisions will be necessary to ensure market/technology viability. Challenges hindering the market from realizing its potential include cell inefficiencies and quality, as well as high manufacturing costs adversely affecting wide technology adoption. What’s more, materials shortage challenges, in particular — silicon — for crystalline cell manufacturing is exacerbating the issue, igniting discussion about alternative manufacturing approaches, such as thin film, particularly given the parallel impact to the semiconductor industry.
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At this year’s SEMICON West, the focus will be on the 32 nm transition, which will include some of the most revolutionary changes in chipmaking history. Scaling beyond 45 nm requires manufacturable solutions for the two most pressing scaling challenges — reducing power consumption and printing smaller geometries. Years of research on these issues have led to identifying viable new materials for the high-k/metal gate and developing new patterning techniques to extend optical lithography.
The complexity of the high-k/metal gate stack revolves around integrating new dielectric and metal materials, and controlling their critical interfaces. Atomic layer deposition (ALD) will be a key technology to meet the scaling requirements of these atomically thin layers. The likely production approach for fabricating the new high-k/metal gate film stacks will be vacuum-controlled, multi-chamber, single-wafer systems, where interfaces and film composition can be tuned and tailored to optimize overall gate stack performance.
Just as the introduction of new material processes enables scaling, the capability to pattern new nanoscale structures must be enhanced as well. Innovative techniques, such as self-aligned double patterning, are rapidly gaining acceptance. This cost-effective, low-risk approach uses a combination of advanced patterning hardmask films and etch processes for printing 32 nm lines and spaces. These steps require new patterning materials, good CD and profile etch control, and metrology that can measure overlay at the feature resolution level.
Transitioning to high-k/metal gate transistors and extending lithographic capabilities are the biggest challenges for 32 nm nanomanufacturing. The good news is that the industry has made huge advancements in these areas, laying down a foundation for years of continued innovation and growth.
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Flip-chip applications and underfill dispensing are still growing at a faster pace than the semiconductor industry. A large increase in flip-chip volume will occur once memory makes the move to flip-chips. This move has been on the horizon for several years; however, the performance benefits for data transfer for DDR5 may be the key application that requires the change from wire bonding to flip-chip for memory.
Pre-applied and no-flow underfills have not proved to be broadly viable alternatives for capillary underfill. In the future, no-lead bumps will put further stress on the development of alternate processes to capillary underfill. Also, these alternatives are not the focus for packaging assembly, because underfill materials and dispensing equipment advances have mitigated the throughput and process control issues associated with capillary underfill. Cost of ownership is still going down while the need for underfill is going up.
The integration of electromechanical devices into semiconductor processes is growing. There is the growth in manufacturing of MEMS, as well as the integration of MEMS devices into products in high volumes. High-volume examples include cell phone microphones and tire pressure sensors.
Wafer and build-up processes are being used to replace mechanical assemblies, like camera modules. One would not consider this a MEMS device, since there is no motion, but an integration of a static mechanical assembly into a wafer bonding and substrate build-up process.
It appears that the growth of solar cells will present new opportunities for front- and back-end equipment suppliers growth, similar to FPD market growth.
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Even casual observers have to appreciate the inventiveness of the semiconductor industry. Whether the challenge is to shrink devices and circuits deep into the nanoscale, squeeze more productivity from manufacturing processes, or put together a business model that successfully contemplates high R&D costs, our industry comes up with winning solutions year after year.
This pattern of relentless innovation will be on display again during SEMICON West’s week of exhibits, meetings, tutorials, demonstrations and informal gatherings. From my perspective, the trends to watch for include:
- The future of 300 mm wafer processing, and industry evolution toward the next wafer size.
- The industry’s leadership in eco-friendly manufacturing, from green fabs to reduced energy consumption.
- Advances in e-manufacturing, process control and metrology — critical enablers for the 32 and 22 nm technology generations (e-manufacturing offers significant reductions in costs, cycle times, process variances, rework and tool downtime.).
- Outlook for extreme ultraviolet lithography (EUVL), and what’s needed to advance from feasibility to manufacturing. EUVL relates directly to the industry’s ability to continue traditional scaling.
- Trends in advanced processes and materials for new devices, and how access to an R&D fab can enhance results.
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Equipment manufacturers in the “value end” of the semiconductor manufacturing process, those who principally make wire bonders and die bonders, intently follow trends in electronic packaging. In the leading edge of the market, emerging packaging methods and novel materials provide the impetus for innovative advanced packaging and interconnection processes and equipment. This continuing evolution in package design is driving significant trends in assembly and packaging equipment.
Smart Adaptability — The “holy grail” of adaptive, closed-loop process control in critical microelectronic assembly processes, such as die bonding and wire bonding, is nearing reality.
Precision Capability — As an alternative to plated-up bumps on die, gold bumps in various configurations, achieving co-planarity of 2 µm, are produced in one pass on a conventional wire bonder. Gold ball bumping will continue to gain popularity for applications where high frequency, high reliability, high thermal dissipation, and an ultraclean process are required.
Thermal Solutions — Dissipating heat from the chip while maintaining satisfactory junction temperatures in ICs, power transistors and LEDs requires innovative heat-sinking techniques and assembly methods. As engineers predict energy densities at the device surface will approach 60 W/cm2, junction temperatures must be regulated to attain higher operating frequencies and increased reliability.
As the enabling technology that thrusts today’s product concepts from prototype into large-scale commercial, military and industrial prominence, automated microelectronic manufacturing equipment and its designers are motivated to solve the problems faced by the packaging and process engineer. They provide the unique solutions that enable microelectronic component production.
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Within the global semiconductor industry, we’ve noticed a growing trend toward addressing adjacent markets. Transferring a company’s proven technology into another market infuses proven innovative solutions to current and emerging challenges, while enabling both time and financial advantages for its customers.
While pursuing “natural” adjacent markets is necessary, it cannot solely sustain long-term profitable growth. The real focus must remain unwaveringly on the needs of customers, addressing both current and emerging requirements. Leveraging creativity and innovation, particularly in the areas of technology and services, is essential to providing added value and competitive advantages for the global customer base.
In today’s global environment, strong customer relationships are critical. Long-term profitable growth is the result of sustained, mutually relevant partnerships with customers that allow us to deliver technology solutions that offer the highest value and quality — no matter what end markets are being addressed.
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Each wafer size transition has provided the IC industry with new challenges and opportunities. Clearly, the biggest opportunity for a wafer size transition is to improve productivity through an increased wafer area, decreasing the cost per chip while following Moore’s Law. The challenge for IC manufacturers continues to be the simultaneous improvements in process control and manufacturing systems, which are necessary to reduce defect density, decrease unit-area process time, and achieve the productivity improvement driving the increase in wafer size.
One opportunity for productivity improvement at 300 mm and beyond is to significantly reduce or eliminate waits throughout the manufacturing process. Waits are delays in the temporal continuity of manufacturing and movement of wafers from one process step to the next. Reduction of such waits can significantly improve manufacturing productivity by increasing equipment utilization and reducing cycle time and work-in-process (WiP). The present generation of automated material handling systems (AMHS) using overhead transport (OHT) systems is based on a fab-wide roving loader, which both transports and loads FOUPs onto equipment loadports. This architecture leads to scheduling challenges and waits in synchronizing FOUPs with empty and full OHT vehicles, as well as with equipment requirements for delivery or pick up. A new AMHS architecture can be developed, which combines the merits of conveyors and vehicles. Such systems would need to provide vehicle-free, high-speed, fab-wide transport, eliminating the wait for a vehicle inherent in the current OHT systems. Such an architecture would reduce delivery times, increase equipment utilization and reduce WiP — thereby improving manufacturing productivity and reducing cost.
The path to next-generation 300 mm manufacturing, as envisioned in the 300 Prime initiative, requires a new architecture for automation, which eliminates waits, thereby improving manufacturing productivity.
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Keeping pace with next-generation consumer applications continues to fuel innovation and increase advanced device developments. Whether the primary design objective is to optimize low-power operation, speed, form factor or cost of advanced consumer products, the implementation plan must consider the relatively short product life cycle and the rapid and timely introduction of the product to a high-volume manufacturing environment. Close collaboration within the industry supply chain, from product integrators to device manufacturers and equipment vendors, is critical in developing the advanced processes and technologies to meet stringent manufacturing and time-to-market requirements.
This year’s SEMICON West will highlight the big advances at the two extremes of the manufacturing cycle, front-end-of-line (FEOL) applications and systems-in-a-package (SiP).
For sub-65 nm FEOL applications, the challenges associated with the successful integration of an increasing number of new materials need to be overcome. New integration schemes and device types, such as flash to phase-change memory (PCM) and magnetic random access memory (MRAM), need to be considered to maintain the benefits of feature size reduction. To solve these new material challenges, techniques such as atomic layer deposition (ALD) can be used to achieve continued device scaling. Because of the complexity of the integration sequence, collaborative R&D among the IDM and foundry communities and equipment and materials suppliers will be a prerequisite for continued success in the development of smaller, faster, cheaper and increasingly complex ICs.
Increased and converging functionality in consumer applications is also driving the adoption of integrating more ICs in one chipset through SiP technologies, which can complement system-on-a-chip (SoC) advances and circumvent the need for costly and time-consuming new SoC designs. Here CDs tend to be of the order of several microns, not several nanometers. For example, “above IC” passives, such as aluminum nitride-based bulk acoustic wave RF resonators, high-k capacitors, and copper inductors to through-wafer vias (TWVs), in which a copper plug vertically connects one die to the next in the Z direction and enables the elimination of some wire bonding steps, can allow additional functionality to be added to products with limited advanced CMOS development.
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As the semiconductor industry pushes up against the physical limits of process technology, and process variability becomes a first-order design concern, there are too many factors that come into play for design and manufacturing to remain independent. These factors include the growing complexity of design rules, process variability and extreme sensitivity of process steps to the underlying layout topologies. It has, therefore, become a business imperative to take a holistic view across design and manufacturing to achieve acceptable defect densities and yields within the time-to-market constraints.
Such a holistic solution requires key technical and business enablers. The key technical enablers are an EDA architecture that goes beyond rules-based to model-based; can richly represent the neighboring context for modeling process design interactions; offers concurrent optimization across logical, electrical and physical domains; and integrates both manufacturing knowledge into the design tools and design knowledge into the manufacturing steps. The key business enabler for this integration is a deep collaboration among the main providers in the design chain.
There are several examples of emerging new solutions that reflect the underlying characteristics of the holistic solution. The most notables one is the move from rules-based, where the penalties and trade-offs are not quantized, to model-based physical implementation and verification. Specifically, integration of lithography, CMP and etch effects into the design flow — enabled by the model-based approach — is enabling design teams to prevent systematic yield loss during implementation. Where prevention is not possible, they have the analytical capabilities to detect problems and tools for correcting the design prior to tape-out. Another example involves a shift from random defects limited yield to feature-limited yield. To bridge this gap, diagnostics-based yield ramp and yield learning technologies are getting deeply integrated into the design flows.
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Developments in ion implantation have largely been evolutionary through the past few technology node progressions. Looking ahead to 32 nm, ion implant will play a much broader role in device fabrication, addressing not only traditional doping applications but also fundamental materials issues.
One example is the use of multi-species ion implantation using traditional p- and n-type dopants together with carbon, silicon or flourine to make very shallow and abrupt electrical junctions. This enables device scaling without any sacrifice in performance.
Similarly, many chipmakers are looking at the use of non-dopant implants to reduce the contact resistance of the silicide contact area and for work function modification for advanced gate stacks. For example, ytterbium and gadolinium implants are being explored to adjust the work function of fully silicided gates at 32 and 22 nm. These new materials have never been used in IC production before.
Molecular implantation shows special potential. It accomplishes the heavy doping needed for high-productivity poly doping gate processes. Molecular implants are increasingly used in advanced memory devices, and have potential for the formation of ultrashallow junctions in advanced logic chips. Using molecular implant species rather than single or monatomic ions increases the effective throughput of the process while, at the same time, reducing the effective energy.
Even more intriguing, IBM is investigating hybrid-orientation technology (HOT). A high-dose implant step of germanium or xenon is used to create amorphous areas on the wafer; silicon is subsequently regrown on these areas with a different crystal orientation than the non-amorphized areas. This allows device designers to have the optimal substrate orientation for both p- and n-type transistors on the same substrate to achieve better mobility and improved device speed.
In each of these cases, ion implant is moving beyond its traditional role of adding dopants to a new level of functionality.
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While increased process performance and lower cost of ownership (COO) continue to be the primary goals of semiconductor equipment manufacturers, a growing emphasis on environmental performance will also be apparent at SEMICON West this year. This trend reflects both increasing public concern about the environmental impact of industrial processes as well as the economic benefits of energy conservation in light of escalating fuel costs. This will be apparent not only in processes such as abatement, that are fundamentally concerned with environmental effects, but across the board as part of a general effort to provide improved capability while reducing both economic and environmental costs.
For example, recent improvements in burner design for gas abatement systems have reduced fuel consumption by nearly a half. These systems can also handle increased gas flows while still ensuring the reduction of hazardous waste components to safe levels and preventing the inadvertent formation of noxious byproducts, such as perfluorocarbons and NOx.
Manufacturers are also looking hard at the costs of basic infrastructure. Process equipment generally accounts for ~40% of energy consumption in semiconductor manufacturing, and as much as half of this energy is used by vacuum pumps. Improvements in pump design can generate significant energy savings directly by reducing energy consumption per unit of performance, and indirectly by reducing overall footprint or inlet size to permit smaller, more efficient chambers on process equipment.
Finally, customization and integration improve both economic and environmental performance. For example, a process-specific abatement system that integrates pumping and waste processing functions can be optimized by design for a specific application, providing much better performance and efficiency than a one-size-fits-all approach.
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Current technical and business trends in the semiconductor industry can be described as divergent compared with the past two decades. The driving force in the industry for many years was a relentless pursuit of smaller, faster transistors. Large numbers of companies marched through technology nodes (0.5, 0.35, 0.25 and 0.18 µm, etc.) in unison, launching products within months of each other. This unifying drive has now given way to an array of factors that pull companies in different directions depending on their target market.
High-performance devices, such as microprocessors and high-speed memories, are still driven toward faster speeds and higher densities. Enormous investments in R&D are required to fuel the need for innovations in materials and process technology. Trends within this segment include ultralow-k interlevel dielectrics (ILD), metal gates with high-k gate dielectrics, plus many other new materials. New integrations frequently require new processes for photolithography, deposition, etch and chemical mechanical planarization (CMP). Development is often done on short timelines with no margin for error.
Mature devices represent a large segment that is choosing to step away from the bleeding edge and shift focus toward efficient production with existing technology. Innovative energy is poured into unique designs, optimization of process flows, outsourcing when appropriate, improving yields, and sometimes blending digital/analog/power devices to create unique product advantages. The goal is to build market share and improve profitability in target applications with longer product life cycles.
Emerging devices represent a third segment. These include MEMS, nanotechnology and optical hybrid devices, among others. While not generally based on CMOS transistors, manufacturing frequently relies on equipment and processes adapted from the CMOS world. Creative manufacturing models can be the key to profits, with many of these companies going fabless (at least initially), leveraging older generation fabs, outsourcing critical processes, or taking other steps to minimize capital and still respond to market timing.
Finally, some trends are universal in nature. Semiconductor companies are not unique in wanting to quickly develop and produce reliable products with high yields and the lowest possible production costs. After all…it’s business.
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At this year’s SEMICON West, we expect to see an acceleration of the trend to incorporate pulse measurements as a standard test procedure. This is being driven by advanced technologies in areas such as flash memory, high-power RF devices, and new semiconductor materials. Pulse measurements are essential for testing flash memory, which requires complex wave patterns for characterization and lifetime testing of memory cells, particularly new multilevel cell (MLC) designs with 50 nm or smaller cell sizes for higher-density chips. Pulse I-V testing and signal analysis is also of growing importance for silicon on insulator (SOI), high-k materials, and RF devices, including lateral double-diffuse MOS, and high-power FETs.
In general, shrinking scale, more sensitive devices, and different failure modes in new technologies are mitigating factors in the demand for more and better pulse test equipment. This demand is growing not only in characterization labs, but is also migrating to the factory floor. As expected, the motivators are more realistic models, higher throughput, lower costs, and shorter time to market.
SEMICON West attendees should look for advances in computational lithography, which address systematic yield limiters in sub-65 nm photolithographic processes. At 45 nm, more complex models and through-process-window correction and verification requirements significantly increase computational burden. Dense simulation, process window optimized optical proximity correction (OPC), new compact resist process modeling capability, design-intent aware correction algorithms, and use of CD-SEM contours for calibration allows more accurate correction for manufacturing. Integration of these software tools with specialized hybrid computing platforms using co-processor acceleration, such as the Cell BE processor, reduces turnaround time for full-chip correction and post-OPC verification. Integration of OPC verification tools with CD-SEM inspection tools helps automate the overall verification process.
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SEMICON attendees should also look for expanding design for manufacturing (DFM) solutions that address increasing design rule complexity. Some areas of DFM advancement include litho-friendly design automation and guidance, such as critical area analysis (CAA), automated critical area reduction (CAR), critical feature analysis, and litho hot spot fixing. Advanced layout fill uses density, gradient and magnitude-based analysis for maximum planarity control with minimal parasitic effects. The integration of layout and planarity/thickness models enables electrical DFM (e-DFM) — the ability to accurately predict the difference between as-drawn and as-manufactured electrical parameters. E-DFM helps guarantee that production parts will meet all datasheet performance specs.
SEMICON attendees should look for advanced OPC and DFM tool adoption at major foundries worldwide for evidence that these tools are delivering real value. They will see a trend toward open physical verification and DFM environments based on open access and other interchange standards driven by customer demand for flexibility, best-in-class technology, and protection of their investment in existing EDA flows.
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New manufacturing paradigms, such as immersion and double patterning for lithography, and new materials and processes required for metal/high-k gate-stacks in the front-end-of-line (FEOL), are providing exciting opportunities for process equipment and process-control equipment vendors.
Process equipment manufacturers are gearing up by bringing tools and processes for deposition and etch to enable double patterning while limiting cost of ownership (COO) penalties. Systems for producing sidewall spacer layers for double patterning without the need for additional lithography steps are coming of age, mainly for the memory space. Double patterning also requires new capabilities in dimensional (or shape) metrology for controlling overlay and CDs.
We expect that on the process control and metrology side, emphasis will be on high throughput and high precision systems to accommodate shrinking process windows, along with very advanced modeling capabilities to meet complex structure needs. Market conditions dictate that process technology is transferred between companies across the globe, and metrology equipment providers will focus on their ability to match their tool measurements across sites, bringing to life a new metric — world-wide fleet matching.
New characterization techniques, including X-ray, will provide insight for control of material properties. Areas traditionally supported by hardware-only solutions will be complemented by advanced software solutions that provide higher automation and ease of use.
We are at an exciting crossroads in the evolution of the industry. Implementation of new innovative process solutions to maintain the march to the tune of Moore’s Law will continue to challenge the industry’s supply chain and bring about the introduction of exceedingly innovative tools.
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The semiconductor industry is moving to environmentally friendly processes that use less energy and are safer. The way to do that is to look at minimizing materials, dangerous gases and high-energy-use products to lower energy use, safer materials and reduced material consumption wherever possible.
Other processes that we’re starting to see are the reduction in chemistries for cleaning, moving from strong SC-1 and SC-2 solutions to weaker, dilute SC-1 and SC-2 solutions. We expect to see the next steps as moving from liquid to spray wafer cleaning in the direction of innovation toward vapor and steam chemistries.
Another development is the ability for the semiconductor industry to transfer its technologies into alternative markets like carbon nanotubes (CNTs), silicon solar cells, and MEMS devices. All these processes are moving toward reducing energy consumption in appliances, household and vehicle use. This will be enabled partially by the mass production capabilities of semiconductor equipment to reduce the overall cost of their fabrication and move them from laboratory scale into mass production, playing off the well established OEM supplier base and foundry model. For these three applications, we’re seeing a number of new processes being developed that are crossing over from techniques that were developed for semiconductor processes. They are now being used to increase the performance and efficiencies of these new technologies and reduce the transfer time from development to mass production.
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Energy. How to save it? How to leverage it? How to collect it? Energy considerations are at the heart of every commercial discussion, every technology decision, every business plan. So at SEMICON West 2007, we can expect the energy theme to take center stage.
For those of us in the advanced substrate ecosystem — both as suppliers and as users — this is nothing new. We’ve been espousing this vision for over a dozen years. While chip manufacturers may have initially chosen to leverage the performance benefits of silicon on insulator (SOI), they did so with a strict eye on the power budget. What is heat but wasted energy?
Energy consumption is hugely expensive. If it’s cut in half, as enabled by SOI, the savings are substantial. Whether it’s in a server farm, living room, or a jacket pocket, or whether it’s for an automobile, a lightbulb, dishwasher or some other industrial machine: End users are doing the math. IBM’s recently announced plan to double the capacity of its own data centers without increasing its energy budget is a perfect example of where we’re headed as an industry.
Materials are the launching point for this revolution. The industry recognizes that the benefits of low power are cumulative. Whether they’re moving to 45 nm and addressing gate leakage or using III-V materials for high power or high frequencies, manufacturers can afford to leave no stone unturned.
We see the proliferation of design tools and IP for SOI this year. ARM’s expansion into the SOI ecosystem, for example, enables the fabless community to join the IDMs in transparently leveraging SOI for ASICs. In this new paradigm, energy conservation need not take a back seat to performance.
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The semiconductor industry is undergoing a profound shift as chip performance and form factor grow increasingly critical for all market segments. I believe that the solution to meeting future device shrinks and continuing Moore’s Law begins with improving transistor leakage to reduce power losses. Many of the current technology roadblocks revolve around the transistor, including such challenges as ultrashallow junction (USJ) formation and the introduction of new materials (e.g., metal gates). Advances in next-generation ICs will be enabled by the adoption of innovative, transistor-level solutions.
Inventing and commercializing new technologies is always challenging. The rate of adoption or integration can be frustratingly slow, because changes at the transistor level have long-term implications. A critical technology shift does not happen overnight; rather, it is accomplished in three key phases — innovation, integration and utilization (which, ideally, follows quickly after integration).
As the industry undergoes critical technology shifts, I look forward to the outcome -- the results of these efforts will surely enable exciting new capabilities for the consumer-driven marketplace of the future.
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The role of chemistry in semiconductor manufacturing is evolving as the industry strives to keep pace with Moore’s Law. The need for increased performance and smaller design rules brings greater complexity in device manufacturing, especially on the gate level where molecular chemistry is being applied. As we continuously find innovative materials for next-generation technology nodes, the need for greater collaboration between process engineers, tool manufacturers and chemical companies becomes of paramount importance.
Advanced architectures, such as those seen in today’s memory and logic devices, are driving the development of new precursor and gate dielectric materials. These materials are used to deposit thin films of new dielectrics, barrier layers or metallic surfaces depending on the choice of precursor and the application need. Many of these newly developed materials, which possess high-k values (>50) are very unstable, causing integration problems. Neither OEMs nor chemicals companies can solve these issues independently. Strong collaborative efforts are required to overcome these integration challenges, often leading to the introduction of new or improved process steps or chemical delivery methods for advanced materials.
Going forward, OEMs, chemicals companies and IDMs will directly interface with each other to develop the best chemistries, process technologies and integration schemes for particular applications.
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One of the most prevalent topics of discussion at SEMICON West will undoubtedly be the changing manufacturing landscape, given the number of IDMs that have ceased or significantly curtailed manufacturing operations in recent months. Fabless chipmakers and foundries are thus becoming even more integral to equipment makers’ customer-target strategies. This new paradigm may actually speed development of the all-single-wafer-technology fab we envision, as high-throughput, highly cost-effective production will be more important than ever.
As we, and many others in the industry, had predicted, 2007 is in fact turning out to be the completion year for the transition to 65 nm. Consequently, business at this node continues to escalate rapidly. As 65 nm becomes more volume-driven, it will automatically end the lifecycle of a lot of batch processes, which will no longer be able to deliver the required process quality or cost of ownership (COO).
At the same time, 45 nm development is happening — the critical factor being the expectation that any equipment developed for 45 nm must be compatible with 32 nm. This is the only way equipment makers can be competitive in the 45 nm arena. Everyone knows how long it takes for technology nodes to really become economically viable, and at 45 nm, this is compounded by some of the technological challenges that must be overcome (e.g., front-end-of-line (FEOL) wafer cleaning and resist strip processes), making extendibility to 32 nm a must for equipment makers’ roadmaps.
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While design for manufacturing (DFM) has been a staple semiconductor hieroglyphic for years, its definition and usage remains unclear. With so many companies offering “DFM solutions,” shouldn’t a prevailing industry DFM strategy and standardized flow have crystallized (if not petrified) by now?
One thing is certain: DFM springs from a holistic approach to designing and building ICs. So, in the spirit of holism, let’s expand the definitions of design and yield.
Design ends when the photomask design is decorated with resolution enhancement technique (RET) structures and verified as viable. These design modifications applied to the mask as compensation for unconventional behavior during pattern transfer to wafer directly affect lithographic yield. Since the 180 nm node, mask designs have been altered with optical proximity correction (OPC) to improve the printing process and prevent it from limiting parametric yield. More recent examples are phase shifting and, soon to come, pattern splitting. And since there has been a well-defined strategy and standardized flow for mask-based RETs for many years now, perhaps we’ve actually been using DFM all along and didn’t realize it.
Continuing this expansive approach, other forms of DFM become readily apparent (e.g., the use of dummy structures to improve chemical mechanical planarization [CMP] uniformity). In many cases, the prescription for reducing DFM to practice is to define a manufacturing problem and implement a design approach to address it.
Tying together the myriad DFM solutions in one elegant strategy and one seamless flow is perhaps the holy (or holistic) grail. But recent design for yield solutions offered by several companies now can classify and address multiple yield detractors. So even if the long-awaited holistic solution escapes us, we at least appear to have a viable strategy and a robust flow. And isn’t that what DFM is all about?
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For SEMICON West 2007, we expect the topic of immersion lithography in process and process control to dominate the show.
Immersion lithography has set new challenges in process control, such as wafer edge/bevel defect detection. Applying immersion fluid may cause defects (e.g., particles) to move from non-critical locations at the edge of the wafer to the front side, which is, of course, very critical. Hence, to have early identification of such problems is crucial, and new automated solutions are required. This includes not only the detection of defects, but also the automatic characterization (ADC) of defects.
Additionally, new packaging technologies, such as wafer-level packaging (WLP), are getting more and more popular but require new smart solutions for process control. Infrared (IR) microscopy-based systems, which allow users to look into or even through the silicon, are emerging solutions.
Mask metrology business is still at a high level. New requests have arisen from shrinking geometries and double pattering technology in particular. Therefore, the required specifications for related tools are increasing significantly, triggering new tool generations. We will see the first developments at the show.
Furthermore, we recognize rising interest in electron beam direct write (EBDW) lithography from IC manufacturers. IC manufacturers are confronted with enormous time and price pressure, which is mainly driven by consumer electronics. Fast prototyping and low-volume production will become important for developing process technologies well ahead of the current technology level. Thanks to EBDW’s high degree of flexibility and its excellent resolution performance, it is already possible today to develop processes for emerging technology levels — and to launch products on the market with the required speed.
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With the leading edge of the industry advancing production to the 65 and 45 nm nodes, and developments at the 32 and 22 nm nodes, it is increasingly critical that tool and process reproducibility be controlled to tolerances never previously required. Especially in photolithography, thin films and implant areas, semiconductor manufacturers are looking for metrology controls that allow them to effectively measure process and equipment parameters to new standards of precision. The ability to report, log and track this data to tune their processes to optimum conditions is becoming imperative.
With the introductions of production immersion lithography and atomic layer deposition (ALD) systems, the feedback loop for controlling equipment conditions in process now requires a new and innovative set of solutions. These solutions should enable engineers to control all aspects of their tools, such as robot hand-offs, placements in tool chambers, and critical in situ measurements of showerhead distances and tilts, as well as other tool conditions that have never been reliably and repeatedly measured in the past.
We’ve seen particular interest in wireless technology facilitating precision measurements of the coplanarity of stations, hand-off measurements, targeting, gapping and parallelism conditions. This technology is being adopted in photolithography, thin films, etch, diffusion and implant areas, enabling significant advancement in process and equipment reproducibility at the 65 and 45 nm nodes in fabs worldwide.
The cost of wafer scrap and maintenance downtime will continue to drive the desire to control process and equipment to tighter levels, and as other problems arise that were insignificant to processes above 100 nm, process and equipment engineers will drive new ways to apply precise, wireless, real-time and minimally disruptive metrology throughout the fab. The opportunities have only begun to be tapped.
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We have seen momentum, as well as actions, from the electronics industry using MEMS oscillators to replace quartz crystal oscillators in various applications. At the same time, quartz crystal oscillator manufacturers have become more open to MEMS technologies by either working with MEMS companies to expand their technology reach or adopting MEMS manufacturing processes for quartz crystals to improve product performance. One thing in common, however, is that applying the concept of low-cost, high-volume semiconductor batch processing for the traditional timing industry is the key to success.
Attendees at SEMICON West will see how MEMS resonators can serve as the heartbeat for electronic systems — starting from the design of silicon resonators and wafer-level packaging technologies to the high-volume semiconductor manufacturing processes. With the progress of MEMS technologies, the semiconductor industry not only benefits from the volume for new applications, but also the push for 3-D integration, higher-aspect-ratio, and more controlled mechanical properties.
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More than ever, semiconductor process technology relies heavily on new materials. The future of the semiconductor industry will continue to require dynamic innovation in materials. Chipmakers need new precursor materials to enable critical technologies — materials such as high-k gate dielectrics, improved gap-fill materials, stress liners for improved transistor performance, and advanced precursors for thin-film epitaxy.
The rapid reduction in CDs, combined with the severe aspect ratios found in advanced designs, particularly in DRAMs and flash memories, requires the use of complex lithography schemes to achieve the desired performance. Photoresists and antireflective coatings (ARCs) that contain silicon can help simplify the lithography process by providing superior etch resistance and pattern transfer, even in very thin layers.
Developing new material solutions for sub-65 nm technology nodes requires the integration and optimization of multiple new materials and technologies at the same time. This requires strategic partnering among IC manufacturers, equipment vendors and materials suppliers.
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Every year brings new challenges and opportunities to the semiconductor industry, and 2007 is no exception. There are three industry trends that are shaping product and technology strategies.
Memory manufacturers are rapidly approaching the 45 nm technology node, and copper interconnects will transition to the mainstream for those devices. Lower defectivity is a key issue for memory.
Cost effective process integration R&D is critical to the continued growth and success of the semiconductor industry. As the R&D cost of developing a new technology node now exceeds $1B, many semiconductor manufacturers are taking steps to eliminate redundancy, share risk, and reduce development time through participation in consortia and by leveraging the rapidly growing technical capabilities of foundries. It is also imperative that we adapt our approach to be effective in this changing R&D landscape. We must improve our R&D effectiveness, cost and speed by working more closely with the leading industry consortia.
Device manufacturers are aggressively seeking ways to scale packaging costs while dramatically increasing the functionality, density and performance of the package. These challenges are driving innovative 3-D packaging technologies, requiring a host of new cleaning and materials solutions in areas such as through-silicon via (TSV) formation, via conductors, and adhesive and dielectric materials for wafer-to-wafer or die-to-wafer bonding.
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Economics is the primary driver of the entire semiconductor industry. The world’s manufacturing facilities are searching for ways to continue expanding existing technologies to meet the requirements for 65 and 45 nm processing. As a result, companies are investing heavily in yield management for their current and upcoming manufacturing processes, and I believe we will see more of these types of solutions presented at SEMICON West.
To enable higher yields, bring next-generation technologies to the production level and continue on with Moore’s Law, the industry will need to increase its use of lasers in processing applications. Due to speed and thermal advantages for new materials at the smaller nodes — especially for low-k dielectrics and copper interconnects — I expect to see clear advancements in laser and photonics solutions. Applications in which lasers provide compelling yield benefits are spreading throughout the semiconductor manufacturing chain, with short-term growth and adoption of laser solutions likely to occur in the areas of wafer singulation and annealing. Micromachining for back-end packaging is another key growth area for lasers, which helps eliminate mechanical stress and enables first-time yields.
Despite all of these challenges and the ongoing efforts to tackle them, the main focus must remain on the needs of global customers. Long-term profitable growth is the result of sustained, mutually beneficial partnering with customers. The key to success in today’s industry landscape is to leverage innovation — in services and technology — to provide customers with cost-effective solutions that deliver competitive advantages.
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Now and evermore, the most important trend in the semiconductor industry remains the continuing effort to pack more computing power into less space. Manufacturers continue to scale their processes and devices to smaller sizes. However, there are important new developments in several new directions. Perhaps the most promising for dramatic improvements in performance is the emphasis on 3-D integration of multiple die. New 3-D structures are also playing an important role at the device level with the introduction of entirely new device architectures, such as finFET and multigate designs.
All of these place new demands and growing emphasis on imaging and analytical capabilities in the semiconductor laboratory. Many structures are now well beyond the resolution capability of SEM, resulting in a growing role for S/TEM and TEM in development, control and failure analysis applications. New-generation S/TEMs are much faster and easier to use than their predecessors, and aberration correctors can provide direct image resolution at the atomic scale. Rapid advances in automated focused ion beam (FIB) based sample preparation make high-resolution S/TEM results available in hours rather than days. Cross-sectional imaging using SEM in a DualBeam or S/TEM on a FIB prepared section provides visual and analytical access to subsurface 3-D structures. SEMs can now provide sub-nanometer resolution over an unprecedented range of environmental conditions to allow fast, easy analysis of multichip packages and chip-scale 3-D integration technologies that incorporate a wide range of conductive and non-conductive materials.
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While the industry continues to push front-end processes to make smaller and smaller devices, there are also very interesting developments occurring at the back end, where chip-scale 3-D integration provides a much easier path to packing greater functionality and more computing power into a smaller volume. The current growth in 3-D integration is driven largely by consumer demand for handheld communication and entertainment products that need not only small size but also low power consumption and heterogeneous integration of disparate technologies — logic, memory, radio frequency and image/video capture. Advanced microprocessors are also adopting multichip designs to accelerate the transport of data between logic and memory.
The size range of microelectronic structures is well suited to hybrid microscopy techniques that integrate various imaging and analysis capabilities to address specialized applications. For instance, combining advanced confocal microscopy and scanning probe microscopy provides 3-D imaging and metrology capability that spans more than seven decades of size, from sub-nanometer to millimeters.
Most current-generation 3-D integration uses stacked die with wire bond interconnects. The sub-micrometer lateral resolution and near-nanometer vertical resolution of confocal microscopy are ideal for characterizing probe mark damage that may interfere with wire bond reliability. Several manufacturers have already announced development of next-generation through-silicon via (TSV) technology that connects die directly through the substrate. The size and pitch of TSV interconnects, typically several micrometers, is well matched to the fast, accurate 3-D capability of confocal microscopy. An integrated atomic force microscope (AFM) could provide detailed structural or material characterization of selected features. Alternatively, a microscope might include micrometer-scale flow measurement technology to characterize structure and flow within a microfluidic cooling device that is integrated into the device package.
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The increasing cost and complexity of R&D are driving far-reaching changes in the semiconductor industry -- an industry that collectively invested over $45B in R&D last year. The challenges posed by Moore’s Law have never been easy. However, it is generally accepted that with sub-90 nm R&D, we have entered a completely new regime, marked by great uncertainty about cost and risk and available options for improving R&D productivity.
Driven to investigate new options, some IC, OEM and materials companies have begun using technologies proven to accelerate R&D productivity in other industries. For example, many pharmaceutical, biotech and petrochemical companies are realizing significant improvements in R&D efficiency and effectiveness through the application of combinatorial technologies. These are integrated systems enabling massively parallel experimentation, characterization and analysis. Development programs using combinatorial technology typically benefit from learning rates 10-100x greater than conventional R&D methods. The result is shortened R&D time-to-results, with the added bonus of reduced R&D cost and risk.
Going forward, companies that proactively apply the semiconductor industry’s innovation imperative to their own R&D infrastructure and methods will gain increasing competitive strength. The measure of their success will be shorter cycle times for discovery, integration and qualification, without disproportionate cost and risk burdens.
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Recent advancements in remote connectivity, diagnostics and service delivery technologies enable OEMs to reevaluate product support through their field service organizations at fab locations around the world.
As semiconductor manufacturing sites pop up in growing global centers, capital equipment manufacturers build field service organizations near these sites to provide product support. OEMs hire local staff at these centers, train them to service the equipment in the field, and bring diagnostic information back to the OEM product support team. The ranks of these technicians swell to support each subsequent purchase of tools in a region as support responsibilities grow. It usually takes some time for these field techs to gain the experience needed to keep these machines online 24/7. In the process of troubleshooting, field techs make numerous trips to the fab to collect the data, which is subsequently emailed to product support teams to help them service the equipment properly.
Now, however, OEMs can access their customers’ tools directly in the field, acquiring necessary data through a secure channel. This connectivity enables OEMs to collaborate online with technical experts within their own company, regardless of location, along with customers to ascertain what’s wrong with a tool and, if necessary, quickly and efficiently send a field tech to a customer site with the correct diagnosis of a problem. Therefore, the process of fulfilling customer support needs is now more expedient, and the quality of the response is vastly improved. Moreover, this level of remote connectivity and communication can increase the effectiveness of bringing new tools and processes online.
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During the past two decades, semiconductor markets expanded as the semiconductor industry relentlessly drove unit transistor costs down. The industry approached these market needs for lower cost by focusing on technology node shrinks every 18-24 months and wafer size increases every decade or so. The process equipment suppliers to the industry supported these customer-inspired geometry shrinks and wafer size increases. However, with the exception of evolutionary improvements in system throughput and longer life consumables, the equipment industry contributed little to drive the cost of semiconductor manufacturing down significantly in the past twenty years. The last major change was the introduction of single-wafer processing, which has enabled greater wafer yields, but at the expense of capital cost and throughput.
The industry is now facing greater cost pressures than ever before as consumer-related semiconductor products multiply. The previous decades’ approach to cost reduction will no longer suffice. New radical approaches to cost reduction are required.
Other industries face similar consumer-driven cost pressures. Toyota found a revolutionary approach to this cost challenge with the Toyota Manufacturing System that uses “Lean Thinking” principles. This approach enabled the company to become the most efficient and largest car company in the world. Lean Thinking is about eliminating waste, adding nothing but value, reducing cycle times, and doing more with less.
Today’s process equipment solutions are mainly based on cluster tools that were conceived 20 years ago as a means to group multiple single-wafer process chambers onto a system and then transfer wafers in and out of these chambers under vacuum. Cluster architectures are inherently wasteful of space, prone to throughput bottlenecks, and hard to service because of poor access to process chambers and the wafer-handling platform.
SEMICON West 2007 will be a milestone event with the introduction of the first semiconductor processing system based on Lean Thinking principles. Now there will be another way to drive down the cost of semiconductor manufacturing.
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Like most companies in the equipment business, we see the industry looking flat this year, with some indications of being slightly down during the second half. Unlike many companies, we see this as a great opportunity. When capacity buys slow down, semiconductor manufacturers put more effort and resource into evaluating technologies where there are “weaker” areas identified in their process. Metrology is one such area of concern.
Solving current inline statistical process control (SPC) problems will be critical to enabling manufacturing at 65 and 45 nm and beyond. We currently see four key areas where current metrology doesn’t meet requirements:
- Strained nitride gates: With stress being key to device performance, chip manufacturers increasingly require the ability to determine post-process stress of thin silicon nitride layers on product wafers.
- Barrier layers: Also critical for device performance, standard measurement techniques are struggling to deal with the measurement of sub-100 Å thick metal layers.
- Low-k ILD: Porous low-k materials are proving to be a major challenge for existing techniques, as density is the most accurate way to measuring k-value.
- Metal gates and high-k dielectrics: Given the use of new, high-resistive materials in metal gates and the fact that high-k materials are non-conducting and opaque, the measurement metrology of the thickness and etching is increasingly complex.
These represent four very clear opportunities for mass metrology. From a bigger picture perspective, as the focus switches from capacity to capability, there are a number of emerging technologies, mass metrology among them, that offer critical solutions to manufacturing weaknesses.
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With semiconductor manufacturers beginning their migration toward 45 nm production, the process challenges associated with that node are likely to dominate the discussion at this year’s show. Specifically, the balance of integrating new materials into a process that involves advanced new equipment represents one of the more daunting tasks. Manufacturers are also wrestling with materials that are difficult to characterize and more susceptible to defects. Increasingly, they are discovering that what they don’t know can hurt them. And, the optical tools they relied on for multiple process generations are falling short on providing the rigorous data required to confidently manage their materials integration.
Consequently, they’re turning to techniques that allow them to more efficiently measure, monitor and control critical materials properties. What used to be a stalwart lab function has now moved to the fab, where real-time X-ray metrology tools provide more accurate, vital data on film thickness, composition, profile, bonding states, interface quality and surface condition. The quality of the data is enhanced by direct measurement techniques instead of the “inferred” data generated by optical technologies. Such X-ray tools — first deployed to successfully characterize nitrided gate oxide films -- are now being evaluated for their potential to more precisely characterize films in other advanced application areas.
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Immersion lithography promises to extend the lifetime of optical techniques, but also introduces a whole new range of inspection challenges. Likewise, metal electrodes and high-k dielectrics will enable continued scaling of CMOS architectures, but present new difficulties for both measurement and inspection. Moreover, the massive amounts of information generated as inspection and metrology tools proliferate within the process constitute a daunting challenge for fast, effective data management and analysis.
As always, the industry responds to new challenges with new solutions. Both immersion lithography and metal/high-k gate processes increase the potential for defects at the wafer edge. The complex multi-film stacks can easily delaminate if not properly aligned. Backside contaminants between the chuck and wafer can deform the front surface, causing defocused hot spots during exposure. As these defectivity mechanisms come to light, manufacturers have implemented all-surface inspection and edge bead removal metrology at sensitive process nodes. In final manufacturing, explosive growth in multichip packages using stacked die with wire bond interconnects has fueled the need to inspect bond pads for damage caused by electrical probing that can degrade wire bond reliability.
We are gathering more defect information than ever before. For example, we now routinely detect and classify defects unique to specific applications, such as polish scratches and residual films occurring in chemical mechanical planarization (CMP), that were previously underreported or incorrectly classified. With fast, reliable inspection and intelligent automated analysis, engineers can tune process parameters to eliminate defects and enhance process yields.
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In the race to pack greater performance into smaller spaces, device makers are constantly shrinking chip geometries through deep ultraviolet (DUV) exposures, immersion lithography and other optical lithography enhancements. In addition to these within-the-chip solutions, they are also turning to creative solutions, such as wafer-to-wafer stacking, chip-to-chip stacking and other forms of vertical integration, to provide high-speed, multifunctional devices to users. To enable this new emphasis on the vertical dimension, visitors to SEMICON West 2007 will see many new materials, tools and strategies to pursue techniques such as 3-D IC.
Several new technology solutions will be required to facilitate 3-D IC, including bonding, interconnect, lithography and metrology. In the field of bonding, show visitors will see a variety of new materials, including BCB, polyimides and other dielectrics, all employed on a variety of tool platforms that perform chip-to-chip, chip-to-wafer or wafer-to-wafer bonding processes.
Next, the theme of interconnect materials and equipment will clearly be in view on the show floor. New metals and alloys are under consideration to improve chip speed by shortening interconnect length, and new ultralow k dielectrics and underbump metallization (UBM) are of great interest in the effort to accelerate processor speeds while minimizing power loss.
Lithographic materials and equipment to enable 3-D ICs will also be in plain view. Regardless of the exact methodology chosen, fabricators will face the daunting task of patterning ever-greater topographies. This poses a challenge to the lithography system, where depth of focus (DoF) is typically limited, and will require new tool solutions, such as spray coaters for photoresist coupled with high DoF exposure tools.
In all the above areas of emphasis, metrology will also be needed to measure new film types, determine a greater range of film thicknesses and steps, or even to view inner defects after vertical stacks have been created. These will require new types of optical, SEM, interference-based or X-ray techniques.
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With many chipmakers beginning to look at 45 nm ramp-up plans, a primary topic at SEMICON West will be escalating activity at the 45 nm technology node. Expect special attention to be paid to the development of new materials for 45 nm and beyond: thin films, low-k dielectrics, slurries and, most importantly, photoresists. Success at 45 nm rests on one critical issue: the ability to understand and control process variations. If you can control variations and optimize your process to accommodate them, in both design and manufacturing, you’re going to come out ahead of the pack.
The need to understand variation is spurring the industry to go back to basics — research into the fundamental physics of semiconductor manufacturing. Until now, we’ve been able to get by on device shrinks alone, but we’ll need a much bigger leap in innovation for Moore’s Law to continue. The 45 nm node is truly brand new; immersion lithography will be predominant, and there will be a host of issues related to resist stability and material stability in the transistor architecture. Process windows are going to be very limited, with little or no margin for error. Given the pressure of shorter market windows, devices must have high-entitled yield going into ramp so that they can get to final production faster.
Design for manufacturability (DFM) techniques will be the key to controlling variations. Variation-aware design methodologies that address every level, from the transistor to the interconnect, will predominate; we’ll be able to apply what we’re learning in early 45 nm production to 32 nm processes as well.