Behind the Breakdown of High-k Dielectrics

With the quick pace at which engineers are attempting to move high-k and metal gates into production, scientists are rapidly characterizing the electrical behavior of these new stacks. At the recent International Reliability Physics Symposium (IRPS), Kisik Choi and colleagues of Sematech (Austin) and the University of Texas (Austin) demonstrated the positive effects of introducing a fluorine implant and a bottom interfacial layer for threshold voltage (V_t) reduction in poly/TaCN/AlN/HfSiO_x gate stacks for PMOS applications. They ultimately achieved a V_t of -0.43 V by combining fluorine implantation, a thermally grown SiO₂ interfacial layer and an aluminum-containing interlayer between the metal electrode and high-k.

Achievement of stable, low threshold voltages with high-k/metal gates has been much more challenging with pFETs than nFETs. The Sematech group recently verified that fluorine implantation onto the metal gate/high-k gate stack helps achieve a high effective work function, thereby reducing the PMOS V_t. The fluorine ions are thought to passivate the positively charged defects near the interface with the silicon.

However, other researchers have observed no effect on V_t values from fluorine implants, indicating that the exact distribution and positioning of fluorine in the stack may be critical to final electrical properties. This study compared various interface processes and examined whether a peak concentration of fluorine near the bottom SiO₂/Si interface would best improve reliability by passivating interface defects, as well as nearby bulk defects.

The various stacks tested (Table ) include the insertion of an AlN layer between the HfSiO_x and TaCN electrode, and comparison of an ozone-treated SiO₂/Si interface (OI) with a thermally grown interface (TI). The implanted fluorine atoms tended to diffuse out of the dielectric after heat treatments, and only a small portion of the initial dose accumulated near the bottom interface. This is important because charges residing close to the channel are likely to have a greater electrostatic impact on device parameters, such as V_t.

The AlN layer effectively shifts the V_t by ~180 mV. The authors attributed this to the dipole induced at the SiO₂/HfSiO_x interface by aluminum atom diffusion and accumulation. Other effects of the AlN layer include an increase in interface trap generation and a degradation in mobility, but the fluorine implantation recovers field mobility back to the level of the control. The fluorine implantation and OI reduce the V_t by an additional ~70 mV. The TI further reduces V_t by ~20 mV, giving a low V_t of -0.43 V.

Effective oxide thickness (EOT) values extracted from the C-V curves were 1.53, 1.95, 2.09 and 2.10 nm for control, Al, OI and TI samples, respectively. It appears that the thermally grown oxide promotes V_t reduction without affecting EOT. Stress-induced leakage current (SILC) data shows that fluorine likely passivates bulk and interface defects (Figure ). The thermally grown oxide, because its growth is stoichiometric, will have fewer defects than the OI, so better electrical stability. The V_t shift from fluorine ion implantation is attributed to passivation of positively charged defects in the SiO₂ layer by fluorine atoms, which also leads to higher mobility and breakdown voltage.

SILC data at 2 V suggests that fluorine atoms passivate interface and bulk defects in the high-k/interface layer stack. A thermally grown SiO2 layer improves SILC characteristics because it forms a stoichiometric film with lower intrinsic defect density. (Source: IRPS)

In work out of Liverpool John Moores University (LJMU, Liverpool, UK), IMEC (Leuven, Belgium) and the Catholic University Leuven , M.B. Zahid and colleagues used variable frequency charge pumping to investigate the creation of traps separately in SiO₂ and HfO₂ in an atomic layer deposition (ALD) SiO₂/HfO₂ stack. This analysis was also presented at the IRPS. By independently controlling the pulse low-level timing (discharge timing) and high-level timing (charge timing), they were able to separate the traps in each layer while also viewing the creation of new traps in each layer.

In this study, trap formation followed a power law behavior as a function of time with an exponent of ~0.32 and ~0.34 for SiO₂ and HfO₂, respectively, independent of stress voltage. The value for the creation of HfO₂ traps with voltage acceleration using the relationship VT²CP is nearly identical to the time-dependant dielectric breakdown (TDDB, -30 vs. -27), which confirmed an earlier published model that TDDB occurs when trap density in the HfO₂ reaches a threshold value. VT²CP accurately predicts defect generation down to a much lower voltage than can be measured. Using the model, only one stress experiment is needed to determine degradation at a given voltage, while TDDB tests normally require many measurements to construct a distribution of failure times.

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