Clean/Strip Challenges at 45 nm

At the Surface Preparation and Cleaning Conference (SPCC) held last month in Austin, Texas, Paul Mertens, Program Manager for the Ultra Clean Processing Program at IMEC (Leuven, Belgium), outlined challenges for the 45 and 32 nm device generations. He said the biggest challenges were finding the balance between particle removal and damage; photoresist strip and clean with minimal silicon loss in front-end-of-line (FEOL) applications; challenges with galvanic corrosion in metal gate stacks; and in the back-end-of-line (BEOL), photoresist removal while maintaining effective k. See his presentation as part of our April webcast, Key Challenges in Surface Preparation at 45 nm.

“Today, we can no longer rely just on underetching of particles because we remove too much material,” Mertens noted. “We have to use physical force to assist the particle removal.” The challenge is to maximize particle removal “by making sure the cleaning events are stronger than the adhesion forces to the particles,” yet not so strong as to create damage. Mertens said that more work needed to be done to understand and eliminate the overlap between these different areas. “The key thing is to make the cleaning process more controlled, so that means end up with tighter distributions. That can be done by improving the uniformity of your systems. Also, we need to take care that we don't have some transients that can create spikes, for instance, in the megasonic power supply, which can create a lot of damage in a very short timeframe,” Mertens said.

Avoiding silicon loss during gate stack formation is also critical, and Mertens said it was important to differentiate the requirements of the source/drain (S/D) extension and halo implants vs. those of the S/D region.

Implants for the extension and halo are done after defining the gate stack. Removing the photoresist at this stage could be challenging with 45 nm devices because of the presence of new materials, such as hafnium oxide, and also a metal gate. Implantation levels for the extension are typically 1 × 10¹⁵ cm^-2. “We have to be very careful using some of the chemistries here. People can go away from the ashing to avoid some of the damage here, or let's say the silicon loss, but then they introduce something like SPM [sulfuric-peroxide mixture]. It is quite clear that a lot of these new materials are actually not compatible with SPM,” Mertens said. “A lot of focus is now on solvents, but even there we have to be very careful. Not just any solvent will be compatible with these materials.”

For the S/D regions, high-performance devices are fabricated by etching silicon and replacing it with epitaxially grown silicon (silicon germanium for PMOS devices). This can be doped in situ or, more frequently, followed by a high-dose implant. “The big issue here is not so much the very small amount of material that we can remove — it's not on the Angstrom level. I'm sure we can remove a few nanometers here without any problem. The big issue here is to find chemistries that are compatible with this very sensitive silicon germanium. SiGe is readily attacked by any oxidizing chemistry in an aqueous solution, so again, something like an SPM is probably not the right thing to do,” Mertens said. The challenges are quite different in terms of material loss — a suggestion for future International Technology Roadmap for Semiconductors (ITRS) editions is to make it more specific for spacer implants and junction implants.

The reason why silicon loss is so critical in these applications is that much of the dopant is implanted to a relatively shallow depth, only about 20-25 nm. “If you take a very close look, you see that a very high concentration is present in a very few top nanometers of these implants. These are exactly the ones we don't want to lose when we do our photoresist strip. They are very important to make a very good contact to the channel of the transistor and keep the drive current high and avoid resistance,” Mertens said.

Interestingly, Mertens said he thought the silicon loss specs identified in the ITRS go too far. “The amount of material we could lose is on the order of 1 nm at maximum for the entire process, so maybe half a nanometer per clean would be a good number to put in any future specs. I think today the ITRS is way too stringent [specifying 1-1.5 Å]. That needs to be fixed,” he said.

A potential process challenge for metal gates is galvanic corrosion, which occurs when two conductive materials are in contact with one another — in this case, doped polysilicon atop the metal.

In BEOL applications, stripping is the most critical issue. “We have a very difficult case because the material we want to remove — the photoresist and the residues, eventually — are chemically quite related to the nature of the low-k itself,” Mertens said. “So selectivity is a key issue here. One more thing which is very critical for back end of cleaning in general is we're dealing with low polarity materials, so that means in general they are very hydrophobic, at least if they are not damaged, so that calls also for a high-performance drying technique.”

Find more information on wafer processing.