New Standards, Techniques for Package Thermal Modeling

Miniaturization, performance and functionality trends in the semiconductor industry are decreasing thermal design margins at the package and chip levels. New compact thermal modeling standards, which are expected from JEDEC this summer, combined with the emergence of more advanced modeling techniques, should help solve future chip and package design challenges.

Increasing power density is the main culprit behind the need for new package thermal modeling standards. “We're seeing power densities going up at all levels of design — including the chip, package, PCB and system. This is mainly driven by die-level heat dissipation,” said Sherman Ikemoto, business development manager at Flomerics (Surrey, UK), a supplier of analysis software to the electronics industry.

The problem at the package level, explained Ikemoto, is that most system manufacturers are buying their packages from other companies, and have to track down the information required for thermal analysis. Also, the time scales involved in doing the design and getting the product out the door are shrinking, and they need to remove bottlenecks in the process to meet delivery deadlines. These factors all contribute to the need for more standards.

Two soon-to-be-released JEDEC compact thermal modeling standards, known as the 2-Resistor and DELPHI (Development of Libraries of Physical Models for an Integrated Design Environment) models, are several steps of sophistication beyond the existing standard (Theta-_JA) and offer reliable, in-application junction temperature prediction. “The DELPHI model is the most accurate, while the 2-Resistor model is fairly accurate,” Ikemoto said. “Engineers now have a choice. It's a little more difficult to derive a DELPHI model relative to the 2-Resistor model, however, so we may not see every package being represented by DELPHI.”

Theta-_JA has been in use since the mid-1990s, and has limitations because it's a very simple model. “JEDEC explains that it's only useful for comparing the thermal performance of one package to another, not design work,” Ikemoto elaborated. “It doesn't capture the complex heat-transfer mechanisms found in real packages.”

The 2-Resistor model consists of a junction-to-board resistance and junction-to-case resistance, and provides a coarse junction temperature prediction.

DELPHI is the result of a 1990s research project conducted by a consortium of European companies, which received 50% of their funding from the European Union. This model provides an accurate junction temperature prediction, according to Ikemoto.

Recognizing an emerging need for package and IC co-simulation (Figure) and die-level thermal analysis, Gradient Design Automation (Santa Clara, Calif.), a supplier of full-chip analysis for digital and mixed-signal ICs, teamed up with Flomerics to develop software solutions. The company has created solutions to help chip designers analyze and avoid temperature-induced electrical issues at the chip level, while taking into account the effects of package and ambient conditions.

What happens on the package affects the die and vice versa.

Fine-grain thermal analysis and multi-scale chip-package-environment analysis are among the new approaches to thermal modeling. The temperature data derived from these tools can be used to identify thermal hot spots and verify you're meeting TJ-_MAX specifications, as well as verify that thermal gradients are harmless, and help with sensor placement, according to Edmund Cheng, Gradient's president and CEO. “It can also more accurately determine the thermal effects on critical aspects of IC designs such as power leakage, voltage drop and timing, signal cross talk and timing, and electromigration,” he added.

Packaging engineers often ask how Cheng knows his fine-grain thermal analysis simulations that produce spiky (as opposed to smooth) temperature profiles are correct at the chip level. “The answer is that our simulation has better resolution than any method of directly checking the measurements, such as IR cameras,” Cheng said. “How can we be checked? First, engineers check very simple things to ensure we correlate well. They check our data against their thermal test vehicles — chips that mimic the thermal behavior of these chip designs being prototyped. Then they'll put thermal diodes on the die and see if they have good information on various areas of the chip. If we show exactly the same temperature as that measurement and come up with pictures that are similar to their IR or thermal measurements, it gives us credibility.”

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