3-D Through-Silicon Vias Become a Reality
3-D TSVs will be introduced in production devices with some applications, such as flash or image sensors, near the end of 2007 or early 2008. Cost/performance trade-offs will determine timing for various applications, form factor for others.
By Jan Vardaman, TechSearch International, Austin, Texas -- Semiconductor International, 6/1/2007
One of the hottest topics in the semiconductor industry today is 3-D with through-silicon via (TSV) technology. While many research programs have been underway for years, commercial products have yet to be introduced. What is driving the market for this new technology? What materials and processes will be used? Will vias be formed during the wafer fabrication process or during IC packaging and assembly? What are the limiting factors to the adoption of this new technology?
Driven by the need for improved performance and the reduction of timing delays, methods to use short vertical interconnects have been developed to replace the long interconnects found in 2-D structures. The industry is moving past the feasibility (R&D) phase for TSV technology into the commercialization phase, where economic realities will determine the technologies that are adopted. Low-cost fine via hole formation and highly reliable via filling technologies have been demonstrated, and process equipment and materials are available. Even though design, thermal and test issues remain, much progress has been made. For instance, Osmium packaging technology from Micron (Boise, Idaho) combines 3-D TSV interconnects under the bond pads with advanced redistribution layers (Fig. 1 ) and encapsulation technology to minimize footprint in a complete stacked die approach.
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| 1. Depiction of the Osmium technology using 3-D interconnects to create high-density DRAM stacks (left). X-ray image of a dual- column two-DRAM stack RDLed to a standard JEDEC BGA package configuration (right). (Source: Micron) |
Many research programs
3-D with TSV options include stacked wafer, die on wafers, or die-on-die structures. Research programs in 3-D TSV technology have been underway for years. Institutes, research organizations and universities include CEA-LETI (Grenoble, France), Cornell University (Ithaca, N.Y.), DARPA (Arlington, Va.), IME (Singapore), IMEC (Leuven, Belgium), Fraunhofer IZM (Munich, Germany), Lincoln Labs (Lexington, Mass.), the Massachusetts Institute of Technology (MIT, Cambridge, Mass.), North Carolina State University (Raleigh, N.C.), Rensselaer Polytechnic Institute (RPI, Troy, N.Y.), RTI International (Research Triangle Park, N.C.), Sematech (Austin, Texas), Tohoku University (Sendai, Japan), University of Arkansas (Fayetteville), and others.
Companies with 3-D TSV research programs include Elpida (Tokyo), Fujikura (Tokyo), Hitachi (Tokyo), IBM (Hopewell Junction, N.Y.), Infineon Technologies (Munich, Germany), Intel (Santa Clara, Calif.), Micron, NEC (Tokyo), Oki Electric (Tokyo), NXP (Eindhoven, Netherlands), Renesas Technology (Tokyo), Samsung (Seoul), Sanyo (Osaka, Japan), Sharp (Osaka, Japan), Sony (Tokyo), STMicroelectronics (Geneva, Switzerland), Tezzaron (Naperville, Ill.), Toshiba (Tokyo), Ziptronix (Research Triangle Park, N.C.), and ZyCube (Tokyo). Many additional companies also have research activities.
A growing number of research consortia are being formed, each focused on a different aspect of the technology or infrastructure. The work of these organizations is critical in the commercialization of the technology.
One of the earliest consortiums was established with government funding in Japan. The organizers of the Association of Super-Advanced Electronics Technologies (ASET, Tokyo), a five-year research program, focused on a new system architecture to provide improved performance. The program was sponsored by the Japanese Ministry of Economy, Trade and Industry (METI, Tokyo), and started in September 1999. It included researchers from 18 companies, including Fujitsu (Tokyo), Toshiba, NEC, Oki Electric and Renesas Technology. Many of these companies are now commercializing products.
Sematech's activity started in 2005 with an investigation of technology options. A cost model was developed, and a 3-D roadmap was drafted for the International Technology Roadmap for Semiconductors (ITRS). The program is currently focused on tool and process benchmarking. Future activities will focus on development of a 3-D infrastructure, materials, unit processes, integration and reliability.
The new EMC-3D consortium includes equipment providers and materials companies, and is focused on addressing both technological and economic issues relative to the development of TSV technology. The cost-of-ownership goal for the integrated 3-D process is $200 per wafer.1
TSV processesOperations in the 3-D integration process include through-wafer via formation, deep via etching, laser-drilled vias, deep trench capacitor technology, via filling, deposition of diffusion barrier and adhesion layers, metallization, and wafer thinning, dicing, alignment and bonding. Figure 2 shows major technologies related to TSV.
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| 2. Processes for through-silicon vias (TSVs) are related to creating the interconnects between the devices (deep trench RIE or laser drilling), filling the interconnects and creating metal bumps on the surface. (Source: S. Denda, Nagano Prefectural Institute of Technology) |
There are currently three process sequences available for the formation of through-wafer vias for wafer-level 3-D devices.2 In a front-end process sequence, vias can be fabricated using deep trench capacitor technology at any fab capable of embedded DRAM technology, before transistors and interconnect are processed on the chips. Such chips would subsequently go to semiconductor packaging houses where backside thinning would expose the bottom of the vias and allow backside interconnect formation. This sequence places the burden of via formation in the hands of the fab and eliminates the need to leave room within or between cells for post-fab via creation.
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| 3. Through-wafer connections are formed using vias etched into the top of the chip, then bonded to the wafer in a chip-to-wafer stacking scheme. (Source: Tohoku University) |
The third process sequence is used when chips not specifically designed for 3-D integration are stacked. In this sequence, the connecting vias are formed by redistributing pads into the area between the peripheral pads and via streets. Vias are then etched and filled in these natural exclusion zones.
No single process has emerged as the most popular process. However, many companies in Japan with early applications have demonstrated structures with the via-last process using polysilicon. Figure 3 shows an example of a TSV structure using a via-last process with polysilicon or chemical vapor deposition (CVD) tungsten, where the via is fabricated from the top.3
Alignment and bonding are key issues for wafer-to-wafer 3-D integration. Wafer bonding requires high-temperature uniformity with high uniformity of pressure across the wafer (1% uniformity across a 200 mm wafer). Such uniformity is achieved through specialized heating chucks with double-sided heating to control the temperature of the wafers and the gradient across the stack. EV Group (Schärding, Austria), SUSS MicroTec (Garching, Germany) and Toray Engineering (Tokyo) supply wafer bonding equipment. The key to these unit operations is to separate the alignment and pre-bonding from the bonding process. Some companies have elected to use bumps between the layers, including solder, indium or stud bumps. In a stud bump connection approach (Fig. 4 ), chips are connected electrically and mechanically at room temperature and elevated pressure. With the chip face down, the gold bumps are formed on the chip I/O using a stud-bump bonder. The gold is deformed and pressed through the hole, and makes a connection to the chip below through an interposer.
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| 4. In this approach, gold stud bumps on the upper chips are pressed through the TSVs on the lower chips. (Source: Hitachi). |
The emerging market
The market for 3-D integration includes many applications ranging from imaging products and memory to high-speed logic and processing applications. Some 3-D integration is planned for military-related products. Applications are expected to include wire-limited circuits, such as gate arrays, systolic arrays, memory and imaging. The main driver is denser circuitry that results in improved electrical performance.
Many companies, especially ones in Japan, see the first applications as all-digital consumer applications — especially mobile phones, digital cameras and digital video products. The first applications for TSVs are likely to be flash memory and image sensors. Requirements for smaller size packages for consumer products are driving the adoption, but potential cost saving is also a driver — especially for camera phones and digital cameras. Oki Electric and ZyCube have announced an agreement to commercialize a high-density, low-profile image sensor with a height of <0.6 mm.
Samsung explains that for NAND flash, conventional cost reduction approaches (mainly smaller design rules) are having less effect in increasing capacity in a given chip size. For this reason, the company is considering vertically stacking flash memory cells on a single silicon wafer, using 3-D technology to maintain the current pace of cost reduction.4
Some companies are also targeting TSV technology for DRAMs, including Elpida, NEC and Oki, with commercial products expected by 2009 or 2010. Samsung has announced a new TSV technology combining 2 Gb DRAMs to create a 4 Gb dual inline memory module (DIMM) that is smaller, faster and uses less power. Tezzaron also expects its first commercial production in DRAM applications. Micron has discussed the use of TSV technology for both memory and image sensors.5
In logic devices, some of the first applications are expected to be in field-programmable gate arrays (FPGAs), where memory may be stacked on top; several companies have already made prototypes. Combinations of microprocessors and memory are also expected in the future. While some examples will be introduced for niche applications in the next few years, high-volume commercialization is not expected before 2009 or 2010, because new processor architectures must be developed.
A bright futureTechnologically, TSV structures can be fabricated. Tools and unit operations are reasonably mature. Yield and manufacturability will develop as the industry scales the operations. Cost/performance trade-offs will be one of the major factors determining timing for some applications, form factor for others. 3-D TSV will become a reality for flash or image sensors by early 2008.
| Author Information |
| E. Jan Vardaman is president and founder of TechSearch International Inc. , a provider of licensing and consulting services in semiconductor packaging since 1987. She is a member of IEEE CPMT, SMTA, the Fabless Semiconductor Association and SEMI. |
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