Package-on-Package Technology Evolves

Package-on-package (PoP) technology has only been around for a few years now, but it's an integral part of the handheld market that's quickly evolving to keep pace with demand for smaller and thinner packages. As Oleg Khaykin, chief operating officer of Amkor (Chandler, Ariz.), noted, “It looks like the industry has overwhelmingly thrown its weight behind PoP technology, and is moving away from the package-in-package.”

This 3-D technology, in which two fully tested packages are stacked during the board mount process, eliminates costly known good die (KGD) issues and provides handheld makers with the flexibility to “mix and match” memory and logic — even from different manufacturers — as needed for particular phones or markets.

Presently, one of the main benefits of PoP technology is the ability to test a component to ensure it meets the desired parameters and is indeed a good part — before putting it down on a board. “There's a real benefit to stacking packages and soldering the leads of the terminals together,” pointed out Jim Walker, vice president of research, semiconductor manufacturing at Gartner Dataquest (Stamford, Conn.). “You can take them apart to repair them if there's a problem.”

How does it work? The top PoP usually integrates stacked memory devices in a fine-pitch ball grid array (FBGA) configuration, while the bottom package typically contains a logic device of some sort (Figure). “Handset makers are buying these packages and reflowing them together onto cell phone boards simultaneously,” explained Flynn Carson, STATS ChipPAC's (Singapore) director of emerging technology for 3-D packages. “They can design PoPs that are fully tested and have burned-in memory and fully tested baseband or logic. All of the major handset makers are either using or are going to be using PoP, combining the logic baseband or ASIC processor with memory.”

The bottom PoP has land pads on the top periphery of the package surface to enable stacking of a second FBGA or top PoP above. (Source: STATS ChipPAC)

One challenge on the technical side is that design compatibility of the top and bottom PoP packages is critical to avoid solder reflow issues. “Controlling warpage is a key factor during the reflow process,” Carson said. “These fairly large thin packages need to reflow together to the motherboard simultaneously. Subcons have a good understanding of which material sets and design rules should be used to control or make warpage of the bottom and top packages compatible so that the total solution will realize high yield in production.”

How is PoP technology evolving? “There's lots of pressure to make the overall package stack solution thinner — to meet a height goal of 1.4 mm,” Carson explained. Right now, PoPs generally have an overall package height of <1.6 mm. STATS ChipPAC is in production with 75 µm die thickness, but Carson said they're looking at moving to 60 µm thickness and thinner. Die-attach materials, substrate materials and mold caps are also evolving along with PoPs for reduced overall thickness.

Most PoPs in production today are 12 × 12 or 15 × 15 mm in size, and are in the process of being reduced. This requires reducing the ball pitch of both the bottom and top packages. “The typical bottom PoP package has a 0.5 mm ball pitch, and a typical top PoP package has a ball pitch of 0.65 mm. And that's shrinking as we try to reduce the size of the package,” Carson said.

The ball size that can be used in the standoff between the bottom and top PoPs is also shrinking. “This is a real challenge when the top PoP package reflows with the bottom PoP package, because it has to clear the mold cap of the bottom PoP package that houses the die and wire bond. That's being squeezed and is also driving flip-chip to reduce that height,” Carson explained. “If you flip-chip the die, you can reduce it. And flip-chip for the bottom PoP package is being driven for performance reasons as well. Two things are driving flip-chip: One is the performance of the bottom PoP package, and the other is trying to reduce the height of the device mounted on the bottom PoP package.”

Taking the PoP evolution further, STATS ChipPAC recently developed a Fan-in PoP solution with a design that accommodates multiple die and larger die sizes in a reduced footprint and the ability to stack off-the-shelf memory packages with center ball grid array patterns on the top surface.

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