Silicides Support Advanced Gate Stacks
After 40+ years of polysilicon/oxide gates, the industry is making a challenging transition to high-k/metal gate stacks. What we are seeing is the end of an era.
By Ruth DeJule, Contributing Editor -- Semiconductor International, 5/1/2007
Silicidation, historically used in contact metallization, is at the center of an ongoing competition among three leading candidates for high-k/metal gate integration schemes, in an industry goal to extend scaling to 45 nm and beyond. After years focused on demonstrating viability, the research is coming to an end. In accordance with the International Technology Roadmap for Semiconductors (ITRS), 45 nm technology is transitioning to manufacturing (Fig. 1 ). By year's end, device manufactures will announce which advanced gate scheme they have selected. Now begins the process of making the systems manufacturable.
The silicide to emerge as most suitable for advanced gate stacks is nickel silicide (NiSi). It was initially introduced at 90 nm for reasons of embedded SiGe source/drain (S/D) stressor compatibility, and generally accepted at the 65 nm node for S/D and gate contacts. NiSi offers slightly lower resistivities than its predecessors in the fab, cobalt silicide (CoSi2) and titanium silicide (TiSi2). Moreover, it forms at low temperatures, with resistivities that do not change as linewidths narrow, and consumes less silicon during silicidation. This last advantage becomes increasingly critical as junctions become more shallow. For manufacturing, NiSi poses challenges such as poor thermal stability at process integration temperatures and high diffusivity.
High-k/metal gate schemes
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| 1. A researcher holds a wafer processed using IMEC's sub-32 nm CMOS research platform. (Source: IMEC) |
The other two approaches — replacement gate and fully silicided (FUSI) gate — place the gate last in a process flow. Both follow a fairly standard processing sequence up to the point of S/D silicidation. With the FUSI scheme, S/D silicidation is performed separately from the FUSI process at the gate. Following gate patterning, the hard mask is left on, covering the S/D and gate. A FUSI module is dropped in between S/D silicidation and contact formation, consisting of an oxide deposition, chemical mechanical planarization (CMP), and reactive ion etch (RIE) to open only the gate. Nickel is then deposited on the polysilicon and annealed until fully silicidated.
The replacement gate approach is the most costly and complex of the choices — complexity on the order of a two-metal gate-first process with topography. As with FUSI, a standard flow precedes metallization, thereby avoiding exposure of the metals to front-end thermal processes. However, the similarity ends after S/D silicidation, where a metal electrode replaces poly and oxynitride through a very narrow opening. A gate metal is deposited and planarized by CMP.S/D silicidation is used in all three schemes, while FUSI has an additional gate silicidation process.
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| 2. Illustrated are the cross-sections of three high-k/metal gate approaches: MIPS, replacement gate and FUSI. |
The goal
Ultimately, the goal of the high-k dielectric is to continue reduction of the effective oxide thickness (EOT) while keeping gate leakage under control. And, ultimately, a metal gate is intended to solve the poly depletion effect, an artifact of ultrathin gate dielectrics and high-channel doping. It creates a change in the depletion layer near the polysilicon/oxide interface, which in turn creates a voltage drop across the poly gate. The result is a reduction in channel current and degradation in device performance. With metal gates, there is no poly depletion problem. The expectation is that metal gates are more easily compatible with high-k material, allowing further scalability to smaller linewidths.
Metal gates solve a big problem, but finding the right material poses a considerable challenge in itself. It all comes down to the work function.
Work functions
Every metal has a characteristic work function, the key material parameter that affects device threshold voltage (Vt).
The difficulty with finding a metal with the right work function is that the effective work function changes with materials processing. Any thermal treatment, oxide deposition, charges and electric dipoles can shift the work function of a material. It is hard to predict what material will have the right work function at the end of the required processing steps. In-depth experimentation is required to understand the interaction of each material with the other materials present during the remainder of the flow. If NMOS and PMOS metals are required, the issue is compounded, potentially impacting Vt and, therefore, device performance.
MIPS
There is nothing straightforward about high-k/metal gate technology. According to Serge Biesemans, director of FEOL technology at IMEC (Leuven, Belgium), “Solving two problems can create two new problems.” For example, the high-k/metal process itself can alter the target Vt or affect compatibility with thin EOT. The road is not a straight one. Ideally, simple schemes that can avoid high temperatures are more easily manufacturable.
Manufacturing is intrinsically tied to the final product. If the product fails, the process fails. From a purely processing standpoint, MIPS appears like that simple scheme — that is, until the need for two different metals became apparent. Moreover, the real problem sets in after patterning the gate, where it is exposed to multiple thermal steps from deposition and S/D anneal to back-end processing, thus changing the properties of the material — most of all the effective work function. Clearly, device performance is the showstopper. With fewer issues, the other two high-k/metal gate approaches face their own challenges.
FUSI
Everyone is doing silicidation. The cost is low, and it requires no new elements and very few extra tools. “FUSI is another silicidation process that you can insert. From an integration perspective, all the materials that you need are ideally available in the fab. It becomes a pure integration activity,” Biesemans said.
Though an advanced gate decision has yet to be made, the resulting simplicity of FUSI has the interest of Texas Instruments (Dallas). “FUSI's simplicity allows for roughly 2× fewer steps in the process flow, compared to other metal gate schemes,” said Judy Shaw, manager of 45 nm process engineering at TI. A further advantage is modularity. FUSI can be implemented into the flow without affecting the other process steps. This eliminates costly, time-consuming reoptimization of critical front-end-of-line (FEOL) steps such as gate etching. A typical process flow can be seen in Figure 3 . Modularity also provides the flexibility to run FUSI with both high-k and oxynitride dielectrics, and makes it very compatible with other performance enhancement techniques for high-performance devices. These include silicon germanium (SiGe), dual-stressed etch-stop liner, and the stress memorization layer.
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| 3. A typical gate-last FUSI flow, followed by conventional processing steps. |
Modularity aside, FUSI still faces manufacturing issues — a small process window. To make FUSI manufacturable requires advanced process control and inline monitoring to control defects, thermal budget and grain structure. All are related to the fact that nickel is a predominant diffusing species that easily reacts on a polysilicon material. Runaway problems can occur, for example, when the silicidation process does not stop right at the gate dielectric. Minimizing this problem requires surface preparation to remove the availability of particles and excess metals before and after metal deposition and when annealing takes place.
The grain structure of the polysilicon is controlled during deposition. Adjustments in temperature, gas flows and pressures control the chemical vapor deposition (CVD) reaction and, thus, the grain structure of the poly that is grown. When fully silicidated, the structure of the resulting film depends on the thickness of the metal. Surface preparation helps ensure that the metal is deposited to the correct thickness. Finally, to obtain the correct resulting work function, nickel and silicon must be in the right ratio.
High-performance FUSI?
FUSI has successfully demonstrated its viability in achieving devices at the targeted threshold voltages, in part because of the compatibility of the NiSi gate metal to the current high-k material, hafnium silicate (HfSiON). With all the thermal issues surrounding it, NiSi is capable of providing the right work function. Questions remain, however, on whether FUSI can achieve a low enough Vt to provide the high drive current that is necessary in high-performance devices. TI, however, is more optimistic, believing it can get high-performance devices from FUSI.
The biggest challenge for high-performance applications is meeting the needed work function for both NMOS and PMOS simultaneously. To have the threshold voltages sufficiently low and supporting the short channels needed for high performance, the work functions of the metals NMOS and PMOS need to be well differentiated, <4.2 and >5 eV, respectively. According to Scott Johnson, manager for 45 nm device and process integration at TI, “We have seen work functions demonstrated that are compatible with the threshold needed.” Internally, TI has created CMOS flows and improved current drive capability on those FUSI transistors over their baseline polysilicon gate process (Fig. 4 ). The work functions demonstrated were compatible with the targeted Vt. But before any of this can be realized, a major challenge of the FUSI flow must first be met to simultaneously optimize the silicidation of the NMOS and PMOS gates.
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| 4. Cross-section of the fully silicided polysilicon gate (190 nm pitch) from an NMOS transistor, processed in a 45 nm high-performance technology CMOS flow. |
NiSi annealing
Controlling the amount and thickness of NiSi formed requires keeping annealing temperatures low — <300°C. In the early days of nickel, when the temperatures were high, the metal directly above the silicon was first consumed while the metal over the surrounding dielectric layers did not react. Instead, it would start diffusing over to surrounding narrow structures, providing an infinite source of nickel. This unintentional FUSI could fully silicidate a polysilicon gate, even when the intension was only to form a thin layer.
Annealing NiSi is normally a two-step process. The first low-temperature, rapid thermal processing step (RTP1), forms a metal-rich phase of Ni2Si. A wet strip removes unreacted metal from the surface. A second RTP anneal forms the monosilicide NiSi, a low-resistance silicide. Overheating may cause oversilicidation, which leads to excessive gate stress, forms the higher-resistivity NiSi2, and increases contact resistance and morphology changes. Conversely, undersilicidation may result in unacceptable variations in Vt and impact yield.
Equipment manufacturers, such as Applied Materials (Santa Clara, Calif.), were motivated to developed sub-300°C rapid thermal anneals (RTAs); for example, radian plus for annealing NiSi. Presently used in FUSI silicidation, the anneal is followed by a low-temperature soak, which removes unreacted metal from the surface to prevent nickel on the dielectric layers from diffusing over to form excess silicides.
The lamp-based RTAs may soon be joined by spike RTA and laser technologies. Spike RTA has been successfully demonstrated for contact applications. Will it be applied to FUSI and the other advanced gate schemes? According to Gary Minor, Applied Material's CTO of front-end processing, “All of the annealing applications are being looked at for millisecond-type annealing in the future. Today, those are predominantly being added onto the existing RTP sets.”
Replacement gate
From a performance standpoint, replacement gate is very attractive for achieving a final work function for both NMOS and PMOS gates, which has been demonstrated at low temperatures. When metal gates on high-k dielectric films with the right work functions and Vt are heated, work functions will shift to the unusable range in the middle of the band gap. The resulting rise in Vts lowers device performance. Threshold voltages can move from 150 and 200 mV to 400 and 500 mV after heating. Obtaining high-performance Vts at the right dielectric thickness while withstanding high-temperature annealing is the key performance issue. Replacement gate avoids these parameter shifts by putting the important materials in place after the S/D junction is formed. This leaves a 450°C budget to contend with, making it more likely to demonstrate the right transistor characteristics. Essentially, the challenge is manufacturing.
In replacement gate technology, the key manufacturing challenge is removing the oxynitride through a very narrow opening (~25 nm wide) and replacing it with a high-k dielectric and metal electrode without creating damage. Once in place, deposition of the high-k and metal layers within the structure requires conformal, ultrathin film formed by atomic layer deposition (ALD), a technology more familiar to DRAM. ALD is capable of depositing sub-monolayers in a back-and-forth motion, with each individual step self-limiting, resulting in a very conformal and uniform reaction.
The number and complexity of deposited layers typically increase with each technology node. Gate stacks at the 65 nm technology node contain four steps: oxidation, plasma nitridation, thermal anneal and polysilicon deposition. For high-k dielectrics, much of the same atomic layer engineering is required to get the right composition and interface characteristics. High-k dielectric itself is going to be a four- or six-step process, which may pose other challenges for the fragile replacement gate structure.
Beyond 45 nm
Scaling beyond the 45 nm node will be a challenge. At 32 nm, the Vt and EOT will need to be scaled, which is considered doable. Further, the system will need to be compatible with high-strain engineering. This was successfully demonstrated at 45 nm requirements, but it is likely the industry will want to add more stress at 32 nm.
The FUSI scheme is expected to meet the requirements of 45 nm, and has been shown to be compatible with first-generation high-k material, hafnium silicate. Whether or not it will be compatible with the next-generation material is an unknown. Still, with work underway, FUSI's scalability concerns may see new light.
The next-generation high-k dielectric will likely have an increased concentration of hafnium. And it is known that additional hafnium can affect the attainable work function. However, according to TI's Johnson, “The science for controlling the work function in NiSi and the other silicides is rapidly developing.” He noted that in the past year, the ability to improve the work function differential between NMOS and PMOS has been “pretty dramatic.” It remains to be seen if the next two generations will see work function and control capabilities overcome the influence of hafnium.
Replacement gate appears to have all the advantages: compatibility with higher-k scaling, thermal budget, relative ease in finding the right material, and obtaining the correct Vt. However, will its fragile structure withstand the additional strain needed below 45 nm for performance? And will a complicated integration scheme and cost be limitations? Companies will decide based on its products, product margin, revenue, extra processing costs, and how long they want to continue to scale.
