IMEC: From MuGFETs to Carbon Nanotubes

Since 1984, IMEC , one of the leading international research and training centers in the field of nanoelectronics and nanotechnology has been located just outside Leuven, Belgium. There, researchers collaborate with scientists from Flemish universities and higher polytechnical schools, as well as with experts from the international semiconductor industry. The scientific research that they engage in runs three to 10 years ahead of industrial needs, and is primarily focused on the production and packaging of ICs and system design.

As semiconductor devices continue to become smaller and more complex, development costs have skyrocketed to a level at which no single IC manufacturer can afford them. The solution is collaboration with others in the market to share the efforts and costs of the necessary R&D in a pre-competitive environment, such as that of independent institutions like IMEC and academia. There are currently over 500 companies and institutes worldwide collaborating with IMEC. Aside from its own personnel, the center accommodates hundreds of researchers from universities and companies. Approximately 1500 people from more than 50 countries work on R&D projects of importance to the industry. On their end, IMEC's industrial partners ensure that these researchers have at their disposal the most modern and up-to-date equipment. Last year, the organization's operating budget was $304.9M.

IMEC is well equipped for hosting R&D for production processes for the next generation of ICs. In its 300 mm research facilities, activities are organized as a series of programs looking at <45 nm CMOS technologies. The 300 mm cleanroom is equipped with front-end-of-line (FEOL) and back-end-of-line (BEOL) equipment. Apart from research on logic, there is also a strong focus on advanced memory concepts. Participants perform cost-effective advanced research that is two to three generation nodes ahead of current manufacturing technology. In 2006, as the semiconductor industry labored to mainstream 45 nm into the development stage, research at IMEC focused on 32 nm and beyond. This includes new materials' research for high-k dielectrics, metal gates, low-k interconnect and ultraclean processing, as well as advanced device concepts such as ultrashallow junctions, strain engineering, spintronics and other alternative device concepts.

ASML's EUV Alpha demo tool being installed at IMEC.

In the area of gate stacks, for example, major progress was attained with nickel-based fully silicided (FUSI) gates. The work demonstrated that nickel-based FUSI would be ready as a manufacturable and reliable process for 45 nm. Focus of the effort was on the more scalable metal gate integration option, metal-inserted polysilicon stack. Several strain techniques, both in planar and MuGFET devices, were also researched, often in combination with gate stacks. These included the use of strained silicon germanium (SiGe) in PMOS source and drain (S/D), the use of strained compressive and tensile contact etch-stop layers for PMOS and NMOS devices, and the application of silicon carbide (SiC) in NMOS S/D.

Research into new lithography techniques and their applications is a cornerstone of the semiconductor technology effort. The organization has made major progress in immersion lithography, and installed the world's first extreme ultraviolet (EUV) tool. Last year, IMEC reoriented its lithography program to research options for 32 nm half-pitch requirements. Over that time, their research in hyper-numerical-aperture (NA) immersion litho investigated the use of high-index liquids other than water. The goal aimed to drive the NA to 1.55, 1.60. Several of these liquids were screened in the ASML (Veldhoven, Netherlands) immersion interface printer, and their potential effect on lithography was predicted.

IMEC's research efforts are concentrated on all the technologies needing development to continue the progression of Moore's Law.

EUV is a major investigation area. The work is centered on ASML's EUV advanced demo tool, which promises extendibility to 22 nm and beyond. A Tel Clean Track Act12 was attached to it for work with resist cleaning, tool assessment and reticle handling. Double patterning work has been carried out as part of the research into 193 nm immersion lithography, which is generally viewed as a bridge to 32 nm, while hyper-NA immersion and EUV lithography are readied for production. The feasibility of double patterning immersion for the 32 nm node has been demonstrated, with encouraging results obtained by splitting gate levels of 32 nm half-pitch flash cells, as well as logic in two complementary layouts. Results seem to indicate that the 193 nm immersion tool, which has a maximum NA of 1.2, might be extendable beyond the 45 nm node.

If most predictions are correct, CMOS will have reached its scaling limits by ~2022. Internationally, research groups are exploring possible routes beyond silicon and CMOS to continue Moore's Law's progression. A major research area at IMEC is the study of high-mobility substrates, such as germanium and other III-V materials, to replace silicon in specific applications. Carbon nanotubes (CNTs) and their application as interconnect are under study.

IMEC is currently developing a large-scale batch manufacturing technique for growing CNTs on silicon. The prime focus is on using these structures for interconnect applications. This requires obtaining an understanding of the fundamental growth mechanisms of CNTs, the target being the selective growth of isolated, controlled-length CNTs on metal catalyst.

The research facility reports that this investigation explored a large group of metallic catalysts and growth conditions, providing important insights into the choice of synthesis conditions and catalysts. This data was also transferred to patterned growth. The selective deposition of large ordered arrays of metallic nanoparticles was used to demonstrate the growth of nanotubes on full wafers. Control over density, diameter, length and location was demonstrated — a crucial need on the road to integrating this material into silicon technology.

IMEC operates not only as a research facility, but also as a training center. Fast-track technological progress requires ongoing training on new developments, not only for participants, but also teachers, university staff and researchers from the industrial world — all of whom can take these advanced courses. The presence of international top scientists and the availability of advanced equipment ensure the maximum utility of these training programs. An important objective for IMEC is to get students interested in nanoelectronics research. This begins at the college and university level; students who wish to submit a thesis or attain a doctorate in nanoelectronics, or the technologies needed for semiconductor systems, are welcomed. Looking forward, IMEC also targets younger students at elementary schools.