Ziptronix, Raytheon Prove 3-D Integration of 0.5 µm CMOS Device
Laura Peters, Senior Editor -- Semiconductor International, 4/6/2007
Direct bond interconnect (DBI) technology has been successfully used to achieve high-density vertical interconnections in a five-metal level CMOS device with silicon PIN detector devices for high-performance imaging applications, including focal plane imagers and high-performance sensor arrays. The 3-D interconnect technology uses an interconnect pitch as small as 10 µm with typical interconnect widths of 2 µm and alignment accuracy of 1 µm (Fig. 1). The Raytheon Vision Systems (RVS) parts were built in a die-to-wafer format. The 100% interconnectivity allowed a 100% pixel operability focal plane, as demonstrated by the 1 Mpixel image (Fig. 2).
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| 1. Cross-section of focal plane array part bonded with die-to-wafer direct bond interconnect technology. (Source: Ziptronix) |
DBIs are formed by a covalent bonding method to create high-strength, hermetic bonds between chips at room temperature. The metal interconnect points of each chip are first exposed using standard chemical mechanical planarization (CMP) techniques. Then, as the chips are bonded, either in a wafer-to-wafer or die-to-wafer fashion, the high bond energy draws the respective exposed metal contact points close together automatically, forming low-resistance, electrical interconnections between the chips. Aside from a short anneal, no externally applied heat or pressure is needed for bonding, so the alignment accuracy can be preserved.
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| 2. Image captures with the focal plane array. (Source: Ziptronix) |
According to Winfried Bair, vice president of business development at Ziptronix Inc. (Morrisville, N.C.), the DBI method can achieve higher bond strengths than competing methods (1 J/m2), therefore allowing the wafer to be made thinner. He estimates the wafer processing cost per wafer for thermocompression bonding at $89/wafer, whereas the DBI method is currently running at $23/wafer. Thermocompression bonding typically requires applied force at 400°C over 40-50 minutes.
But the true advantage to the method is the integration capability within the assembly supply chain and commercially available bonding and pick-and-place tools. The via-first process is followed by metal CMP, processing at the foundry, then pick-and-place operations. The patented bonding technology is being licensed to foundries so that customers can use the technology in one of two ways: for bonding only (for MEMS, etc.,), or for bonding and electrical interconnect (true 3-D processing).
Such 3-D approaches will help integrate MEMS with ICs, RF components and mixed-signal devices, and bring memory closer to logic cores.
