IITC Preview: New Materials Reduce RC Delays

Peter Singer, Editor-in-Chief -- Semiconductor International, 4/1/2007

The 2007 IEEE International Interconnect Technology Conference (IITC) will be held June 4-6 at the Hyatt Regency Hotel at the San Francisco airport. A selection of pre-prints provided by conference organizers yields some interesting tidbits, with an overall theme of how "new" materials, such a ruthenium, rhodium, manganese and carbon nanotubes (CNTs), can be used to further reduce resistances and capacitances that lead to RC time delays, which ultimately reduce how fast a chip can run.

Fujitsu (Kawasaki, Japan) researchers, for example, used nanoclustering silica (NCS) to build a full interconnect structure with a good total effective k (k_eff) value. That combined with an ultrathin barrier metal resulted in RC delays 86% less than what's listed in the 2006 International Technology Roadmap for Semiconductors (ITRS) update .

Work at NEC (Tokyo) demonstrated the practicality of replacing tungsten with ruthenium as a liner/barrier. The advantage of ruthenium is that it can be plated on directly, eliminating the need for a copper seed layer, but critics have said it is neither a particularly good barrier nor seed layer. NEC's trick was to change the grain structure of the ruthenium so that its orientation was more compatible with copper, leading to less electron scattering along the sidewall.

Another somewhat novel metal, rhodium was shown to have good qualities for void-free filling of high-aspect-ratio structures at the contact level, where tungsten is still now commonly used. IBM (East Fishkill, N.Y.) demonstrated that using a physical vapor deposition (PVD) titanium/atomic layer deposition (ALD) ruthenium/electroplated stack for the liner/seed/fill results in an overall resistance that is ~2X lower compared with a chemical vapor deposition (CVD) tungsten stack, and slightly lower than copper fill stacks. In addition, the ability to use a thinner liner layer than that used for a copper-base fill process provides a greater potential for extendibility of rhodium fill into future CMOS, the researchers noted.

Sony (Tokyo) researchers have also explored the advantages of another lesser-known metal, manganese. Their method combines copper/ultralow-k interconnects with a self-formed manganese oxide (MnO_x) barrier layer that was shown to have lower resistance and higher reliability than copper alloys. This is a "hybrid" structure, in that it has one dielectric at the bottom of the via and a different one on the top. The researchers reported that dual-damascene interconnects with the MnO_x barrier layer showed excellent stress-induced voiding performance, significantly longer electromigration (EM) lifetime, and required no additional pore-sealing process. They concluded that this self-formed barrier process is the most feasible technology for 32 nm node copper/ultralow-k interconnects.

The challenge of putting new materials -- porous dielectrics in particular -- into standard packages was the focus of a study by NEC. The company looked at its seamless low-k SiOCH stacks (SEALS) technology, which has an k_eff value to 2.9 (Figure ). The SEALS structure replaced all films, except the SiCN capping layer, with lower k value dielectrics. For example, the SEALS used MPS-SiOCH (k=2.5) for the intermetal dielectric (IMD), and replaced the SiOCH (k=2.9) interlevel dielectric (ILD) with porous-SiOCH (p-SiOCH). This structure eliminated the etch-stop layer, resulting in additional reduction of the effective k value. The group's conference paper describes the chip-to-package interaction related to the SEALS interconnects. In addition to the wire-bonding reliability, the impact of the coefficient of thermal expansion (CTE) of the epoxy molding compound (EMC) for the quad flat pack (QFP) and plastic ball grid array (PBGA) package was investigated. They also examined the thickness effects of both the epoxy molding compound and substrate in PBGAs on low-k stack reliability. Their conclusion stated that adhesion strength of the via-ILD to the lower SiCN capping layer significantly impacted wire-bond reliability. However, spreading the contact area within the fine-pitched bonding pad eliminated the bonding failures in the low k_eff structure. No failure was detected during the reliability tests in PBGA and QFP with a variety of packaging stresses, confirming the practicality of the low k_eff interconnects for 45 nm node ULSI applications.

Designed interconnect structures for 45 nm, called SEALS, along with the 65 nm shrink structure.

Other research out of Japan, this time from MIRAI-Selete (Yokohama, Japan), studied the electrical properties of a CNT via interconnect fabricated by a novel damascene process compatible with conventional copper interconnects. It was found that the resistance of 60-nm-high vias was independent of temperatures as high as 423 K, which suggests that the carrier transport is ballistic. The obtained resistance of 0.05 ohm for 2.8-micron-diameter vias is the lowest value ever reported, the researchers noted. From the via height dependence of the resistance, the electron mean free path was estimated to be ~80 nm, which is similar to the via height predicted for 32 nm technology node (year 2013). "This indicates that it will be possible to realize CNT vias with ballistic transport for the 32 nm technology node and below," they concluded.

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