More 'Grand Challenges' Ahead for Packaging

Echoing the 2006 International Technology Roadmap for Semiconductors (ITRS), the International Electronics Manufacturing Initiative (iNEMI) has identified thin wafer packaging and related stacked die as high-priority grand challenges or "gaps" for the semiconductor industry in its 2007 packaging roadmap. New materials development and substrate technology remain key target areas, not surprisingly, with the common goals of driving costs down and improving performance and reliability.

There's no disputing that thin packaging is "in," but it's bringing along some baggage. Issues that could prove to be either speed bumps or full-on roadblocks and require more research include:

• Wafer/die handling for thin die
• Different carrier materials
• Establishing new process flows
• Improving reliability and testability
• Different active devices
• Electrical and optical interface integration

The rapidly increasing popularity of packaging technologies, such as complex system-in-a-package (SiP), stacked packages, wafer-level packages and lead-free packages, are also spurring the need for integrated standards for reliability testing and product qualification to help bridge the gaps between semiconductor and system standards, according to iNEMI.

Booming demand for SiPs — including stacked die packages, stacked package-on-packages (PoPs), modules and multi-chip modules — means we'll likely continue to see more SiP integration in the future. "SiPs are no longer just for wireless applications," said Oleg Khaykin, chief operating officer, Amkor Technology (Chandler, Ariz.). "Now it's used in networking applications or anywhere you have high-performance or minimal form factor or a combination of both."

On the materials end of things, the transition from 200 to 300 mm is affecting both packaging equipment and processes. Equipment iNEMI identified as experiencing the most difficulties handling the larger wafer size includes those associated with wafer thinning, saw, die attach and flip-chip placement areas.

The industry's need for both new materials and technologies is increasingly important as packaging becomes much more tailored to the application of the advanced silicon (65, 45 or 32 nm), Khaykin noted. "Whether the product is going into mobile solutions or networking gear or gaming makes a big difference, because there are vastly different requirements, aside from protecting the silicon," he said. "For example, in wireless, drop test survivability, the ability to integrate with other silicon, and reduce the form factor are all very important. What we see going forward is a much greater proliferation of all kinds of variants of packaging."

What's on the horizon for substrates? New approaches to substrate fabrication are high on iNEMI's list of priorities (Table ), with the development of electroformed imprint technology and phase-shifted dielectrics recommended as solutions to address the need for dramatic increases in density, reduced process variability to improve electrical performance, and that ever-present need to reduce costs.

Another packaging trend, according to iNEMI, is that wafer-level packaging may help the industry shift to a lower cost structure by eliminating many of the assembly and test processes currently in use. "Wafer-level chip-scale packaging technology is taking on a more interesting role as we push the envelope of die size and I/O count," Khaykin said.

And yet another trend, not necessarily discussed in iNEMI's roadmap, is that nanotechnologies are playing a huge role in solving difficult challenges, such as the need for reducing the process temperature for handling packages and assembling them off circuit boards.

Will we see a huge revolution in the way packaging is put together any time soon? "In the immediate term, the answer is 'no.' I think we're going to see better solutions to assemble incremental-type products," said Alan Rae, vice president of market and business development, NanoDynamics Inc. (Buffalo, N.Y.).

"As we move to finer and finer pitch, things will become more heat-sensitive. As you integrate other functions on silicon, in terms of MEMS devices or sensors, then those will become more fragile. We're going to have to look at the whole issue of how we package devices and put them on the circuit boards, so that we don't destroy them during the assembly process."

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