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Applied's Litho Scheme: Patterning vs. Printing

Aaron Hand, Executive Editor, Electronic Media -- Semiconductor International, 4/1/2007

As a company not known for playing in the lithography space, Applied Materials (Santa Clara, Calif.) would like to remind everybody: Lithography is more than just printing. As outlined by Farhad Moghadam, general manager of Applied's Thin Films Group, at a press luncheon during SPIE's Advanced Lithography conference, the lithography space has expanded past traditional printing (the exposure tool, track system, masks and photoresist) to encompass preparation, productivity, defects, pattern transfer, metrology/inspection and design for manufacturing (DFM) as well.

It's easy enough to imagine why Applied might want you to think of electrochemical mechanical polishing (ECMP) to help with depth of focus (DoF) challenges; or its advanced patterning film (APF) hard mask to achieve reduced line edge roughness (LER) or improve etch selectivity. So hearing that Applied has the solution for printing 32 nm lines and spaces with 193 nm dry lithography might make many a lithographer skeptical. But the semiconductor equipment behemoth has what appears to be a relatively cheap and simple double patterning scheme that could keep flash memory manufacturing in dry litho through at least 2013 — meeting 28 nm flash requirements, according to the International Technology Roadmap for Semiconductors (ITRS) .

Of course, double patterning is the talk of the town in lithography circles these days, with several papers presented on the topic at advanced lithography. The basic idea is to split a dense circuit pattern into two less dense mask designs, effectively reducing the k1 factor to <0.25, the theoretical limit for single-exposure lithography.1 But there are several different variations on the double patterning/double exposure theme, and Applied is proposing one particular to its set of expertise.

1. Applied's self-aligned double patterning scheme uses two layers of the company's APF hard mask along with nitride spacers to create dense circuit patterns. (Source: Applied Materials)

Applied engineers already know that their APF hard mask reduces LER. Although they don't understand the mechanics of it very well, they do know that a typical LER of 4.4 nm is reduced to 2.7 nm with the APF. They also contend that their Enabler etch system can shrink critical dimensions (CDs) by up to 50 nm with good CD and profile control and minimal silicide loss. Putting these factors together, they have

2. In this example, a 32 nm line/space array was produced with a 128 nm pitch on a 193 nm dry lithography tool. Final LER is 1.5 nm. These specs meet ITRS guidelines for 28 nm flash (2013 production). (Source: Applied Materials)
come up with a new self-aligned double patterning scheme that combines APF hard masks and nitride spacers (Fig. 1). In this scenario, lines could be patterned at 64 nm, for example, then trimmed to 32 nm (with a 128 nm pitch). The pattern is transferred into the APF hard mask, where a nitride spacer is formed and etched. The first APF layer is stripped, and a second APF etch is performed, creating a final structure with 32 nm lines on a 64 nm pitch (Fig. 2 ).

Not only does this method enable extreme ultraviolet (EUV)-type geometries with dry 193 nm lithography, LER actually gets progressively better with more APF steps. In this case, it's improved to 1.5 nm. And the nitride spacer step is one that could not be done with photoresist alone; the APF has the required thermal stability, unlike resist, which would just burn away, Moghadam noted.

The Monday of Advanced Lithography week in San Jose, litho toolmaker ASML (Veldhoven, Netherlands) announced its record results for 193 nm immersion and EUV lithography technologies — achieving 37 nm dense lines and 32 nm dense lines and contacts, respectively. "There are other ways to get to 32 nm lines and spaces," Moghadam said, noting that Applied's solution comes with a much lower price tag to boot.


Reference
  1. A. Hand, "Double Patterning Wrings More From Immersion Lithography ," Semiconductor International, February 2007, Vol. 30, No. 2, p. 40.

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