Posturing & Positioning in 3-D ICs

At the fall 2006 Intel Developer Forum , Intel (Santa Clara, Calif.) CTO Justin Rattner described "major innovations" in its pipeline. Multicore technology was front and center with the "terascale" chip — a processor with 80 cores on a single piece of silicon that can deliver up to a teraflop (1 trillion floating-point operations/sec) of computing power. The main problems that go with using an 80-core processor are related to interconnect and memory latency. Rattner emphasized that TSVs allowed the company to achieve terabyte (TB)/sec transfer rates between the processor and memory. He indicated that TSVs could be used in a variety of Intel chips. He also hinted that computer makers could, in the future, get their memory when they bought their processors from the company.

Connecting memory directly to the processor would have huge performance benefits. Presently, memory and processor in Intel-based computers exchange data through a memory controller, which operates at a far slower rate than the processor, making it one of the big bottlenecks in computer performance. TSVs, which would displace the memory controller, move data far more quickly.

That said, the memory chips currently attached to the 80-core processor are SRAM. Intel's next step is to see how well DRAM works with TSVs. Also, since the processor typically generates more heat than the memory, packages with the proper thermal solutions are needed. Rattner concluded that "We will do a lot of work with it [TSV] in the next several years."

At the IEEE 2006 International Electron Devices Meeting (IEDM), Samsung Electronics' (Korea) President and CEO Chang-Gyu Hwang reported in his keynote address, "New Paradigms in the Silicon Industry," on a 1 terabit (Tb) flash chip that could be produced in current footprint. Using the term "fusion technology," Hwang explained that "...the integration of memory, logic, sensors, processors and software will be based on die stacking 3-D technology."

Samsung earlier announced that it had developed a small-footprint, wafer-level processed stack package (WSP) using TSV interconnection technology. Samsung showed a 16 Gb memory solution by vertically stacking eight 50-μm-thick, 2 Gb NAND flash die into a prototype 0.56 mm in height. The WSP has a 15% smaller footprint, and is 30% thinner than an equivalent wire-bonded stacked package solution. WSP also reduces the length of the interconnects, resulting in an ~30% increase in performance caused by reduced electrical resistance. Instead of using a conventional dry etching method, Samsung's WSP technology uses lasers to form the TSV. This reportedly reduces production cost significantly, as it eliminates the typical photolithography-related processes required for mask-layer patterning.

Samsung reported that it will apply its WSP technology to the production of NAND-based memory cards for mobile applications and other consumer electronics in early 2007. The company claims it will extend the packaging technique later to high-performance system-in-a-package (SiP) solutions and high-capacity DRAM packages.

NEC Electronics (Kanagawa, Japan), Elpida Memory (Tokyo) and Oki Electric (Tokyo) announced that they jointly developed new flash chip technology. By using 3-D stacking technology, the memory capacity of a single DRAM package can be increased without waiting for the debut of a new silicon generation. With the new technology, 4 Gb of DRAM capacity is achieved by stacking eight 512 Mb DRAM chips. Because 512 Mb DRAM are already available, the single-package 4 Gb DRAM can be made as soon as the assembly process is in place. This would allow handheld devices to carry as much memory as a computer, and would meet the increasing demands of high-definition video and graphics.

At the Fall 2006 MRS meeting in Boston, researchers from the three companies described how each layer is first reduced to a thickness of 50 µm, then stacked and subsequently connected by forming TSVs drilled from the underside of the silicon and filled with conducting polysilicon. These stacks are attached to a PCB substrate and a controller chip, and then the entire structure is sealed in resin.

Micron's (Boise, Idaho) CEO Steve Appleton has described their "Osmium" wafer-level packaging technology, which he indicated would be applied to both its semiconductor devices and image sensor lines. The technology includes TSVs, redistribution layer technology and wafer-level encapsulation. Memory devices and image sensors could potentially be fabricated without leadframes and substrates reducing the packaging cost, now estimated at 15–25% of the finished product.

E. Jan Vardaman, whose company TechSearch International (Austin, Texas) produced the first market study on 3-D wafer-level IC technology last year, is currently gathering data for a second report. Vardaman noted, "The industry is moving past the feasibility [R&D] phase for TSV technology into the commercialization phase. In conducting research for our new study, we are finding many potential applications, ranging from imaging products and memory to high-speed logic and processing applications."

Another signal that 3-D technology is about to go commercial is the formation of the EMC-3D consortium by equipment vendors Semitool, EV Group, Alcatel and XSiL, in addition to several institutes and materials supply companies. Their goal is to develop 3-D processes that will allow a cost of ownership of <$200/wafer.