Defect Detection Faces Smaller, Deadlier Hurdles

An endemic disadvantage of smaller nodes has been that, as device architectures shrink, defects and particles on the previous node that were unimportant have the potential to become device killers. This, in turn, has device makers demanding greater capability to detect increasingly smaller defects and particles. Although the race between detection capability and shrinking defects has basically been going on since our industry's beginning, now, and in the not-so-distant future, formidable hurdles in the shape of 3-D architectures and fundamental limits challenge inspection, measurement and test platform technology.

Immersion litho complications

Immersion lithography will make life difficult for defect detection. As Ehud Tzuri, strategic marketing manager for process diagnostic and control at Applied Materials (Rehovot, Israel) put it, finding defects is increasingly complicated "not just because of new types, but because of size. Most new defects are large and generally well understood, such as immersion litho-related ones like bubbles, watermarks, etc." These can be controlled to the same extent as with dry lithography, because their sources are known.

Paradoxically, because of immersion lithography's higher resolution, smaller defects are emerging. Over 70% of defects on a wafer are <50 nm. During early characterization, many were missed by earlier tools, not because they did not exist, but because the tool could not detect them. These small bridges, footers and the like are miniscule defects — once ignored or not identified — that can now become significant (Fig. 1 ).

These tiny defects must be detected. "Higher resolution is the best way," Tzuri said. "However, traditional brightfield microscopy, even with DUV, is reaching resolution limits. It isn't possible to resolve a very dense pattern, such as today's NAND flash pattern at <55 nm." Applied Materials' solution uses 3-D collection, combining deep ultraviolet (DUV) with laser illumination with. This enables defect detection in the range of one-tenth of the wavelength.

1. Because of immersion litho's higher resolution, smaller defects are emerging that can be missed using traditional brightfield detection technology (right). This is overcome by using 3-D collection, where DUV illumination allows high-resolution and laser illumination increases the maximum intensity. (Source: Applied Materials)

As the 22 nm node approaches, optical inspection will face problems, making e-beam tools increasingly necessary to detect ultrasmall defects. This requires e-beam to be made more productive by equipping it with production-worthy throughput — an engineering challenge. A combination of optical and e-beam is likely.

Useful destruction

2. A scanning TEM image of an electrical defect clearly shows shorting at the gate. The root cause was not clearly identifiable with cross- sectional TEM. (Source: FEI Co.)

Before the industry reaches 22 nm, TEM must transition from an offline lab technique into the fab. Short-term, the cycle must be shortened to around two hours; long-term, there has to be migration. With strained silicon regions, an importance factor is that the stress on the sample can change when one cuts into the wafer. This will require new TEM preparation techniques that prevent lamella deformation.

How severe defect detection problems become on the road to 22 nm will greatly depend on whether we use today's transistor design — albeit smaller — in which case TEM use will increase; standard cross-sectional SEM and basic top-down CD-SEM cannot measure or quantify what must be looked at. The alternative is finFETs and other 3-D structures. However, these structures cannot be adequately measured by traditional SEM and top-down CD-SEM technology, so some sort of non-destructive technique will be required.

An obvious choice is scatterometry. The question is whether it can handle the finFET structure's dimensions and complexities, and whether cross-sectioning will be needed to build and validate scatterometry's models, or if this technique will ultimately be needed to validate the inline measurements. If it becomes necessary to fully understand what happens with a finFET structure at the 22 nm node, some form of cross-sectioning may become inevitable.

Resolution and materials

Design rule shrinks drive resolution. Tools must provide better resolution to measure defects at or below design rules, especially for logic. Mike Kirk, group vice president of the KLA-Tencor (San Jose) Wafer Inspection Group, believes that this not only drives the optics and their fidelity, but also image-computing requirements because smaller information pixels must be processed. "Since the 0.25 μm days, pixels have shrunk by approximately a factor of three," he said.

According to Kirk, higher resolution evolves slowly because if a 20 nm pixel were to be implemented, the tool would be too slow and costly to operate. "Just as scanner developers have k factors, we have an equivalent we call a defect-to-pixel ratio, which we continuously attempt to improve by finding an increasingly smaller defect for a given pixel size. We must reduce the pixel while getting more information from it. This means better processing, better algorithms and optics that have superior resolution for a given pixel — higher NA," he said.

Another concern is new materials. Determining how a defect may physically appear and then what it looks like optically or electrically is complicated. There are near-field interference effects, dielectrics absorb more or less light, and a tool cannot be designed just for a given layer of a certain thickness with a specific n and k because the user will change requirements for the next shrink or a slightly different device, demanding different optical properties. There must be flexibility in optical systems in both the illumination and detection schema to cope with the different structures or materials that may be employed.

Metrology providers must work closely with fabs during development phases. Device makers do not decide to use a certain material just because it has the desired electrical properties or thermal management budget; they also want to know if it can be inspected, measured and controlled. They make those decisions early during process development, and bring in the metrology supplier to provide tools for advanced materials and design rules to help them choose. "The problem is that they may choose six different things and later decide on just one, so we must help with all six and have the right platform at the proper time," Kirk said. This means performing complex defect and device modeling for the fab during early stages to ensure tools have the right numerical aperture (NA), illumination, wavelengths, angles and collection geometries.

The roughness problem

The problem of <22 nm defect detection and noise rejection is a pending nightmare. When a gate line is made, the pattern transfer is imperfect and the device edges have some roughness. Die-to-die or transistor-to-transistor, there is no perfect uniformity. "The tool picks that up as a defect, and the user doesn't want it flagged until it reaches a size where it does matter," Kirk said. The problem is that no one knows a priori what that size will be. Within that line edge roughness (LER), one might want to find a small footer at a trench bottom. This little protrusion coming out of a line causes a short or leakage; thus, a signal must be picked up from a feature that may be <20 or 15 nm in diameter and is embedded in a sea of LER background noise.

There are other systematic defects produced by reticle design. A slightly aggressive optical proximity correction (OPC) for a certain structure may be repeated several times over the die and, given the process window, occasionally fails. The fab engineer must know this and track it to the design. He also wants to know if there are systematic failures originating from, for example, the etch chamber. It may have peculiar boundary conditions and setup areas where the etch is not uniform across the wafer. Random defects must also be revealed, and those that do not matter are rejected, while systematic problems are also pointed out, and those that originate in the reticle vs. those from the process tool are determined.

According to Rajiv Roy, a marketing director in the Inspection Business Unit at Rudolph Technologies (Flanders, N.J.), "At the 0.25 µm node, one might have used micro inspection tools to overlap with some of the macro inspection platforms to resolve issues of defect detection and review. At 45 and 22 nm, those tools are being used to detect critical defects at 32 nm. One must consider the cost of ownership to find those critical defects that give you the most efficient ROI from the micro defect perspective."

That simplifies the micro inspection rationale. It now becomes useful to filter out macro defects from the micro. Macro inspection is already cost-effective, but it came with review baggage, requiring a human to look at the defects and judge their importance. Today, the technology can perform image capture on the fly. Added to powerful decision-making tools, manual review may be facing extinction. Technology makes a compelling case for high-speed, completely automated macro inspection and review (Fig. 3 ).

3. Advanced segmentation and classification of defects on a production wafer can systematically reduce the number of defects that a human operator or advanced ADC system would have to classify. (Source: Rudolph Technologies)

Mike Plisinski, vice president and general manager of Rudolph's Data Analysis and Review Business Unit, pointed out that converting data into information is an ongoing effort. "We have technologies that reduce the large volume of data generated in today's production fabs into actionable information," he said. "There have always been spatial signature analysis systems on the market, but like ADC systems, they've never been able to provide the performance and ease of use that production requires. There are now algorithms that do this. We've accomplished a 20–30% reduction in what users must review."

The increasing importance of LER and linewidth roughness (LWR) is why a more automated classification engine is needed. An automatic defect classification (ADC) engine can look at what is captured and classify it; if it is a known classification, then the user knows what causes the problem. If unknown, the user will at least know that there is a pattern forming that must be investigated. Without a fully automated system, a human must be involved, and this is time-consuming and yields do not ramp up very quickly.

SEMs have not traditionally had a large focus on ADC. There is ADC for SEMs, but it has only recently become commonplace. This means multiple ADC systems to maintain, which can become a problem. There is a need for an expert system to simplify the analysis.

Overlays and masks

Overlay is increasingly becoming a measurement challenge, as current optical-based methodology approaches its limit. "This isn't a matter of engineering development. It seems difficult to extend the current methodology, and new innovations, such as using SEMs, may become necessary, so substantial R&D will be required," said Jack Jau, executive vice president at Hermes Microvision (Milpitas, Calif.).

Jau agrees that nuisance defects will become destructive as they shrink. "The pattern error or systematic defects, caused by things like improper OPC or smaller process windows, is emerging as a major yield killer. DFM is said to solve the problem; however, it requires a sensor to see the problem to do feedback to design," he said. "It becomes essential to have an effective metrology or inspection tool to act as a sensor."

Mask defects are a prime concern because they replicate. "A single defect on a wafer might disable a single chip," said Ingo Schmitz, senior applications engineer at Veeco Instruments (Woodbury, N.Y.). "On a mask, if it's a killer defect, it can annihilate the entire area of that flash field, up to a quarter of the wafer and, depending on the level, it might ruin the entire wafer."

Two mask repair methodologies have emerged. One is a focused ion beam (FIB) technique, the other uses atomic force microscopy (AFM). The latter is similar to an AFM tool, where a blade-like tip mills away excess material, such as excess chrome, to repair the mask. This makes it necessary to know if the defect is a protruding defect or a pinhole. Optical techniques have difficulties with characterization.

4. AFM image showing three 'stamping' boxes (1.00 × 0.78 µm, 2.20 × 1.70 µm and 3.30 × 2.60 µm), which are elevated by 0.3, 0.9 and 1.7 nm, respectively. The inspection can induce staining, shown as a dissociated carbon defect deposited prior to the AFM measurement. (Source: Veeco Instruments)

Today, 15 to 20 nm size particles are beginning to cause concern. AFM should have enough sensitivity for those smaller particles, and there is probably sufficient technical capability to detect particles as small as 5–10 nm.

If the defect is more optical in nature, such as a watermark, AFM technology is challenged, because it uses a different technique from what a stepper would use. A watermark or stain would cause a misprint, and the AFM, sensitive to topography changes, might not detect it.

SEMs are not exempt from topography-related problems. When defects are characterized by a SEM, the stamping caused by the SEM can induce secondary damage such as a defect, from dissociating chamber components that lands on the mask (Fig. 4 ).

For metrology to continue providing the defect detection platforms needed, the gap between design and manufacturing must be bridged. As designs increase in complexity, systematic defects also grow. Finding these and separating them from random defects to deal with the root cause of the former will become very difficult.