Redistributed Chip Packaging

Just as chips benefit from the size reduction of transistors, so do systems: Reductions in size very often result in increased functionality at lower costs. While silicon chips continue integrating more functionality as per Moore's Law, in many systems the die only represent a fraction of the parts in a system. Advanced packaging technology must address integration of the rest of the system. Also, as silicon integration results in smaller and lower cost devices, packaging and test costs are skyrocketing.

In the late 1980s, we introduced the over-molded pad array carrier (OMPAC) for use in products with space limitations, such as radios, pagers and cellular telephones. Quickly adopted as a standard both by JEDEC and EIAJ under the name plastic ball grid arrays (PBGAs), it became the key enabler for high pin count surface mount technology (SMT), providing an elegant solution to the crucial problem of coplanarity, while allowing for high yield and excellent electrical and thermal properties. Because of PBGA, assembly technology could keep up with the rapid progress of silicon processing and increased product complexity.

With the introduction of redistributed chip packaging (RCP) technology, the industry now faces change of the same order of magnitude. RCP offers unmatched integration density because it reduces both footprint and thickness by up to 30% vs. the traditional PBGA package styles. Key to the size reduction is the integration of the packaging steps as a functional part of the die and system solution. The PBGA replaced the leadframe by a printed circuit board (PCB) substrate, to which the die was electrically connected by wire bonding or flip-chip technology before being covered by a molding compound. RCP takes the next step, eliminating the PCB, as well as the need to used wire bonding or flip-chip bumps to establish electrical contacts. Without a PCB, the package is inherently thinner, without even thinning the die when lower profiles are required. As an example, a 9 × 9 mm package can provide 280 I/O, and is only 0.7 mm thick, replacing a 13 × 13 × 1 mm mold array process ball grid array (MAP-BGA) package.

RCP has a number of inherent advantages:

• Excellent electrical performance, superior thermal properties
• Simplified assembly process, batch processing for potentially lower costs
• Reduced assembly stress, most suitable for packaging modern die with enhanced speed using low-k porous dielectrics for interlayer isolation in on-chip interconnects
• Reduced stress results in increased quality and reliability
• High flexibility in materials and construction to address specific needs of a wide variety of application
• RCP materials make it an ideal "green" product in that it is halogen- and lead-free and RoHS compliant.

Process flow

The advantages of RCP listed above occur via the elimination of wire bonds, flip-chip bumps and the package substrate. In order to do this, the assembly process is modeled after semiconductor manufacturing serial processing, where several devices are packaged simultaneously. Figure 1 demonstrates the current process flow. Singulated die are placed with the active side facedown on a substrate. The die are then encapsulated with a silica-filled epoxy molding compound. After cure, the panel of the die is ground to the desired panel thickness and released from the substrate. The die panelization process is done with standard assembly tools, such as a pick-and-place tool. The epoxy panel with die then undergoes a redistribution process to route out the signals, power and ground. Redistribution is performed using standard silicon manufacturing equipment. These processing steps consist of the deposition of copper metallization layers by electroplating techniques. The metal layers are separated by insulating layers comprised of a spin-coated photoimageable dielectric, and patterned using batch process lithography. The metal layers connect the pads on the die surface to the pads placed on the surface of the package, providing the same function as the metal layers in the substrate of a ball grid array (BGA), but with a much finer resolution. The pads are then provided with a NiAu or solder finish for land grid array (LGA) or solder balls for BGA.

1. In a RCP process flow, the die is placed active side down on substrate and encapsulate (a), substrate is removed (b), signal, power and ground are redistributed (c), BGA solder ballsare deposited (d), and the panel is sawed into individual packages (e).

The number of metal layers in a package is dictated by the package size, BGA or LGA pitch requirement, I/O count, power and ground requirements, and routing design rules. A panel with a 200 mm diameter can hold 82 sites of a 17 × 17 mm package featuring 208 I/O with 1 mm BGA pitch (Fig. 2 ). This package requires two layers of metal for routing. A 9 × 9 mm package in the same 200 mm panel diameter has 300 package sites. At 0.5 mm BGA pitch, this package routes 280 I/O in two layers of metal. The same package size in a 300 mm panel diameter can hold 708 packages. Several different functional products have been built in the RCP laboratory, including a 5 × 7 mm RF transceiver package with 73 I/O using four metal layers, a 7 × 8 mm power management device package with 186 I/O using two metal layers, a 9 × 9 mm baseband processor with 280 I/O using two metal layers, and a 29 × 29 mm microprocessor package with 783 I/O using four metal layers.

2. Packages pictured show shrink capability of RCP from a 13 mm x 13 mm BGA to 9 mm x 9 mm RCP as LGA (center) and BGA (right).

Modeling results

To prove the ultralow-k compatibility of RCP prior to packaging functional devices, mechanical modeling was performed and compared with existing flip-chip PBGA packaging models. The packaging impact to low-k back-end-of-line (BEOL) layers is described by a fracture mechanics quantity: energy release rate (ERR). The ERR is defined as the amount of strain energy (stored in a deformed body) that releases when the crack extends and forms a new unit area (units are J/m²). The fracture model assumes that a small defect preexists in one of the low-k BEOL interfaces. If the external load causes the ERR at the crack tip to exceed a critical value (called fracture toughness), the crack will grow and eventually cause a delamination. If the ERR is larger than the fracture toughness, the crack will grow; otherwise, the crack will not grow. In this study, the defect is modeled as a 2-μ-long crack. The design goal of low-k compatible packages is to minimize the ERR by changing the material, geometry and packaging scheme. A finite element method implementation was developed in-house to calculate the ERR for interfacial fracture based on commercially available FEM software from ANSYS Inc. (Southpointe, Pa.).

The RCP case modeled was a 29 × 29 mm package with 783 I/O and a 12 × 12 mm die with SiCOH interlayer dielectric (ILD). A 2 μm-long crack is put in different horizontal locations to calculated the ERR. The ERR changes greatly near the RCP via edges connected to the die (at -50 and 50 μm). Because of the stress buffering effect of the RCP build-up layer, the BGAs have a very small effect on the low-k BEOL. The ERR of RCP package is compared with that of the flip-chip PBGA and flip-chip HiCTE ceramic ball grid array (CBGA). The RCP is 5× better than the best flip-chip configuration. The lead-free bump effect in flip-chip PBGAs is also studied. The flip-chip PBGA with lead-free bumps induces ~40× higher ERR than the RCP does. If the lead-free bump is required by the legislature in the near future, flip-chip will not be a low-k friendly package. On the contrary, RCP could be one of the best candidates for low-k compatible packages because of its low delamination driving force.

We performed electrical modeling of a microprocessor device to understand the resistance, inductance and capacitive (RLC) differences between RCP and flip-chip PBGA and flip-chip CBGA. Again, a 29 × 29 mm 783 I/O package was used. RCP had four layers of metal consisting of two signal layers, one ground plane, and one split-power plane. The flip-chip PBGA was a 3-2-3 substrate design with four signal layers, one ground plane, and two split-power planes. The flip-chip CBGA was an 11-layer metal substrate with five signal layers, three ground planes, and one split-power plane. The core V_dd and ground were fully routed. The core supply analysis was done using the Sigrity Speed tool. Electromigration (EM) simulation was done in time domain using the finite difference time domain (FDTD) technique. Smooth Gaussian source and optimal resistance was used. Frequency domain was converted using Fourier transform. The RL extraction is from short-circuit impedance. The results indicate that the inductance and F_max of RCP is better than flip-chip PBGA and similar to flip-chip CBGA (Table ).

EM simulations were also run to compare the lower cost wire bond devices typically packaged in MAP-BGA against the electrical performance of RCP. A 280 I/O 13 × 13 mm MAP-BGA with 0.65 mm pitch can be shrunk to a 9 × 9 mm RCP with a 0.5 mm pitch. Estimated lead inductance in the MAP-BGA wire bond package ranges from ~4 to 12 nH. Estimated lead inductance in RCP package ranges from ~1.25 to 3.5 nH. This represents a potential lead noise reduction theoretically as high as 70–75%.

Thermal performance of this new package is a concern for high-performance products. To model the thermal performance, a 25 × 25 mm, 360 I/O RCP package is placed on a four-layer, thermally enhanced board in a JEDEC standard environment. The individual dielectric layer of the RCP substrate is modeled as individual blocks with effective thermal conductivities based on series/parallel thermal resistance networks. The ambient temperature is maintained at 25°C in 1 ft³ enclosure; the simulation solves for both thermal and hydrodynamic (flow) fields. The silicon die was 9.9 × 8.5 mm. The die is encapsulated, and the backside of the die/encapsulant is ground to 0.7 mm thick and exposed. The die surface dissipates 1 W of uniform heat. The objective of the study is to predict junction-to-ambient thermal resistance under various flow conditions and package options, and to compare it to the thermal performance of similar flip-chip BGA packages. Several flow conditions and package configurations were examined: natural convection, no copper lid on the die/encapsulant backside; forced convection at 1 m/sec (200 ft/min), no copper lid; natural and forced convection with copper lid; natural and forced convection with copper lid and heat sink; and natural convection with thinner RCP layers.

The baseline natural convection RCP case indicates a peak temperature of ~46.4°C, corresponding to a junction-to-ambient thermal resistance of 21.4°C/W. The similar forced convection case (1 m/sec) leads to a thermal resistance of 15.9°C/W. Compared to the 25 × 25 mm 360 I/O flip-chip PBGA, the RCP achieves better thermal performance under both natural and forced convection conditions. The incorporation of copper lid on the die/encapsulant backside not only increases the convective heat transfer from the lid, but it also improves the heat spreading across the entire RCP footprint. This results in ~27–30% reduction in the junction-to-air thermal resistance (in both natural and forced convection environment), as compared to cases without lid. With both lid and heat sink in forced convection, the best thermal performance (R_ja=2.33°C/W) is achieved. In this combination, the package is capable of dissipating ~27 W (at an ambient of 85°C) without exceeding the peak junction temperature of 150°C. The thermal performance degrades further when reducing the copper layer thickness in the RCP substrate because of the lack of heat spreading. Changes in dielectric layer thickness have little impact on RCP's overall thermal performance.

For consumer products used in cell phones, PDAs, MP3 players, etc., drop testing is of significant interest. All new packaging technologies for these products are concerned with drop test performance. At Freescale, drop test is assessed using a dynamic four-point bend test. Packages are placed at 45° orientation to drop test board, resulting in higher stress and strain in the board and solder joints. Both LGA and BGA packages have been simulated, and there has been good agreement between prediction and empirical data. Comparing simulation results of a 13 × 13 mm 280 I/O MAPBGA and the same device in a 9 × 9 mm 280 I/O RCP show that the RCP is capable of exceeding current MAPBGA drop test results. When the same is done for a 5 × 7 mm RCP in the same size as its LGA package counterpart, RCP exceeds the LGA simulation results.

Reliability data

Reliability studies were done on a 9 × 9 mm 280 I/O RCP with two layers of metal. The package passed MSL3/260°C preconditioning, 1000 cycles -40° to 125°C air-to-air thermal cycling (AATC), and 96 hours of unbiased, highly accelerated stress test (HAST). These tests are currently being run to failure. Upcoming reliability studies for the 9 × 9 mm RCP include MSL1/260°C, MSL2/260°C, -65° to 150°C AATC, biased HAST, high-temperature operating life (HTOL), temperature-humidity bias (THB), high-temperature storage (HTS), board-level reliability (0°-100°C AATC) and drop testing. In addition, reliability testing is planned for a 5 × 7 mm RF transceiver package (four layers of metal), a 13 × 13 mm baseband processor package (three layers of metal), and a 29 × 29 mm microprocessor package (four layers of metal).

Target markets

RCP was designed to be applied across multiple product spaces. This versatile package has a large number of variations, and can be optimized for the particular application requirements. For example:

• RCP is usable for single-chip, multi-chip and system-in-a-package (SiP) assembly
• RCP can easily support package-on-package (PoP) stacking
• RCP is compatible with the cavity packaging required by some types of MEMS, etc.

RCP's exceptional versatility makes it easy to adapt to 3G mobile phones, as well as a broad range of consumer, industrial, transportation and networking systems that can be miniaturized by further integration and consolidation of the number of parts in the system.

Single-chip products that can immediately benefit from RCP advantages include network processors like PowerQUICC or digital signal processors of various types. Likewise, RCP technology can be applied to application-specific circuits, among which single-chip products for wireless communications include application processors, baseband processors and power management circuits. Furthermore, multi-component modules are easily realized using RCP to build radio-in-package (RiP), RF tranceivers, or power amplifiers.

We exemplified the power of RCP technology by building a RiP containing all the electronics of a i.275 GSM EDGE platform radio — memory, power management, baseband processor, RF transceiver and power amplifier — that is approximately the size of a postage stamp and <25 mm on a side (Fig. 3 ). An electrically functional i.275 GSM EDGE RiP module was also built with memory, power management and baseband in RCP and the RF transceiver and power amplifier in existing packages. Since existing packages were larger than they would be in RCP, the electrically functional module was slightly larger than a postage stamp at 25 × 25 mm. The memory was embedded in the bottom RCP package, while the other RCP packages and the modules were stacked on top, demonstrating not only RCP single-chip capability, but also PoP and SiP.

3. An i275 GSM EDGE radio-in-package using RCP.

Acknowledgements

Thanks to Jeff Zhao, Rob Wenzel, Victor Chiriac and Vijay Sarihan for mechanical, electrical, thermal, and drop test simulations, respectively. Thanks to Andreas Wild for the packaging background, and to George Leal and Trung Duong of the RCP team for providing cover art.