High-k, Metal Gates a 'Go' for 45 nm

In a surprise announcement described as the “biggest change to computer chips in 40 years,” Intel (Santa Clara, Calif.) said it has committed to putting hafnium-based high-k gate dielectrics and metal gate electrodes into production for the 45 nm generation. Intel's announcement was quickly followed by a similar one from IBM (Yorktown Heights, N.Y.). The two advantages of a high-k gate dielectric over the silicon oxynitride now used are reduced gate leakage and increased drive current. It also enables future scaling, since conventional dielectrics are already critically thin, measuring only ~5 atoms thick. It's estimated the almost half of a chip's power consumption is due to current leakage through this thin dielectric.

Texas Instruments (Austin, Texas) announced last June that it would be putting metal gates into production for the 45 nm node , but at the time said that continued use of proven silicon nitrided dielectrics would deliver the necessary power consumption control without having to simultaneously move to new, more complex high-k materials.

Intel said it remains on track for 45 nm production in the second half of this year. The announcement is surprising because the latest International Technology Roadmap for Semiconductor (ITRS) , which includes input from Intel and IBM, forecasts a delay of two years for high-k and metal gates, pushing their introduction from 2008 to 2010.

Several different types of high-k materials have been evaluated for use as an alternative gate dielectric, but most research has focused on hafnium-based solutions, and that is what Intel and IBM have said they will be using. Problems such as Fermi-level pinning and adhesion have so far delayed the introduction of high-k gate dielectrics, but both Intel and IBM say they have solved those problems.

Presently, most electrodes are highly doped polysilicon, but they are not compatible with high-k dielectrics. Intel has previously announced that researchers have demonstrated dramatic performance gains using gate electrodes with work functions tuned specifically for the n-channel and p-channel transistors used in CMOS chips. The company has remained highly secretive about the exact composition of those metals, however, as well as when they might be employed in production, saying only it will use “a combination of different metal materials for the transistor gate electrodes.” No details were released on how the metal gates would be fabricated: straight deposition of the metal, or a less radical fully silicided (FUSI) approach.

Sematech (Austin, Texas) engineers have also announced that they have demonstrated high-k/metal gate stacks that were used to build high-performance NMOS and PMOS transistors in a CMOS configuration (Figure ). This was a continuation of work announced last year, where the consortium identified effective NMOS materials for metal gates and had previous success with developing high-mobility high-k dielectrics. The PMOS and NMOS materials were successfully integrated into highly scaled CMOS devices that showed low threshold voltage (V_t) similar to conventional polysilicon/SiO₂ devices, and ultrathin equivalent oxide thickness (EOT) in the range of 1.0–1.2 nm. These CMOS devices were fabricated with conventional gate-first, high-temperature processing flows, with no reduction of drive currents or other performance metrics. In addition, good performance was demonstrated without using substrate counterdoping or other extraordinary or complicated measures.

Transistors with high-k gate dielectrics and metal gates offer the advantages of reduced gate leakage and increased drive current. Optimal performance is obtained by selecting metals with work functions respectively tuned to either PMOS or NMOS. (Source: Sematech)

Bernie Meyerson, vice president and chief technologist of IBM's Systems and Technology Group , said the technology had become a fundamental differentiator. “We're already running high-k metal gate chips in our fab in Fishkill, and they've been running for quite some time to go through all the qualifications. What's happening is we've announced that we are actually formally doing a couple of things: One, we've sent out papers on this and expect a flurry of activity; the second thing is we're actually going out with a form of high-k where we raise the bar a lot over where people have been.”

Myerson said the real news is that the process has been perfected to the point where it is a “drop-in” replacement for SiO₂. “The challenge has been, historically, these materials have been to say the least, delicate. As a consequence of that, people have not been able to do them as drop-ins…they've had to do all sorts of exotic processing and go back and reinvent the whole flow of the transistor process. The version that we're going to go out with, not only is it a drop-in — literally a one-to-one swap-out with the SiO₂ — but it's also a significant advance in terms of being able to drive the actual T_ox [the equivalent oxide thickness] down dramatically.” IBM is not releasing specifics at this time, but plans to do so in a paper to be presented at the Symposia on VLSI Technology and Circuits in Kyoto, Japan, in June.

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