Sidewall Metrology Expects Clear Sailing to 32 nm

As semiconductor technology evolves toward the 32 nm node, there is some concern whether traditional metrology solutions such as CD-SEM, scatterometry, atomic force microscopy (AFM) and others will continue providing those measurements that are crucial to process development and control. While there is every indication that CD-SEM and scatterometry will be capable of measuring CDs at the 32 nm node — and AFM has measured CD lines <25 nm — continuous improvement will be necessary to meet the requirements imposed by each succeeding node.

Bob Monteverde, director of marketing at Timbre Technologies (Santa Clara, Calif.), thinks a significant benefit of optical digital profilometry (ODP) is that it is a true profile measurement, not just a top-down image or CD measurement. “ODP gives a complete profile: CD at the structure's bottom, at the top, and the sidewall shape,” he said. For simplicity's sake, fabs have traditionally distilled the profile shape metric into a single CD value for use in statistical process control (SPC) and advanced process control (APC). However, in advanced processes, the control of profile shape is increasingly critical, and improved sidewall information is necessary. Serguei Komarov, senior applications engineer at Timbre, works on complex 3-D aspect-ratio applications. He views sidewall angle (SWA) metrology as important because a small angle change results in a huge alteration in dimensions with high aspect ratio. “Destructive cross-section measurements aren't production-worthy, and top-down CD-SEM cannot provide true sidewall information. ODP gives accurate sidewall shape measurement. As to extendibility, at 32 nm we can show performance with 3-D applications on very high aspect ratios.” (Fig. 1 )

1. Fabs have traditionally distilled the profile shape metric into a single CD value for use in SPC and APC. In advanced processes, the control of profile shape is increasingly critical, and improved sidewall information is necessary. Instead of obtaining profile information from destructive cross-section measurements, ODP provides profile information non-destructively. (Source: Timbre Technologies, courtesy of ISSM 2006)

Scatterometry performs dense line space measurement best because it uses a periodic grating. As lithography is driven to make dense features with increasingly smaller linewidths, ODP advances provide detailed metrology for emerging lithography techniques, such as double patterning. For litho process control, SWA is a focus indicator. Previously, when using CD metrology for process control in lithography, CDs were measured, and the dose on the scanner was adjusted to tune the CD to the right size. With ODP providing both the CD and SWA measurement, there is the capability to monitor both dose and focus.

The progression to 32 nm is challenging. With 3-D transistors, structures with dimensions that were lateral are now vertical, making profile metrology critical. A gate is no longer represented by the lateral distance between the structure's right and left edges; it is the distance along the vertical wall.

At 45 and 32 nm, with traditional scaling unable to keep up and with technologies like finFETs and double patterning (which metamorphose overlay into a CD problem), profile measurements and SWA are the link between lateral and vertical measurements. If they vary, they affect one another through the SWA. These two measurements are now inseparable, requiring a complete profile measurement and understanding of how these metrics interact.

Major challenges for sidewall metrology lie in deriving repeatable and accurate methods to assess line edge roughness (LER) and sidewall roughness (SWR), and separately characterizing them to reduce process development times. “As gate lengths drop to 30 nm, LER will become a significant part of the CD budget, and must be characterized and controlled,” said Dean Dawson, senior director of marketing for automated AFMs at Veeco Instruments (Santa Barbara, Calif.). Excessive linewidth roughness (LWR) can cause device failure and CD measurement uncertainties. Performance of new device structures will be affected by excessive SWR. Additionally, SWR of low-k materials requires characterization to overcome porosity and copper electromigration issues.

Profile accuracy of critical features becomes necessary at 45 nm to overcome CD-SEM and scatterometry bias issues. Accurate profile metrology also provides calibration and regular monitoring of scatterometry models, enabling their use as a stable production metrology tool. Sidewall metrics, such as LER/SWR, are essential for 45 nm processing, and may be adopted as process control monitors.

Recent 3-D AFM scanning technology improvements and a new CD “finger” probe design now enable high-resolution, accurate measurement of SWR and LWR over the entire profile. LER has been assessed by SEM technology, which is limited in its resolution and measures from the top down only. Prior to 3-D AFM, the only methods for assessing SWR were to take a horizontal TEM along a feature, or cross-section trench features and measure with an AFM. Both are costly, time-consuming and lack a statistical basis for process development. Additionally, 3-D AFM enables accurate profile and angle metrology, including undercut features. Reference metrology for profile is significant because of bias issues on current CD metrology systems.

In recent years, SWA control has become increasingly important. “Gate litho is the most critical layer for SWA control. For example, given a typical 45 nm node logic gate, a 1° change in SWA results in approximately 1 nm final gate CD change. SWA must therefore be controlled to much less than 1°,” said Wayne McMillan, director of marketing at KLA-Tencor (San Jose). “Scatterometry technology enables cost-effective SWA measurements in production.”

An abstraction of SWA control is profile control. Most tools measure and control profile in production with scatterometry technology. Typical applications running in production today include shallow trench isolation (STI), spacer, gate recess etch and back-end-of-line (BEOL) trench.

Using spacers to control the transistor's electrical performance is becoming complex. There are now multiple spacers, and the deposition and etch of each determines where the implant occurs. Fabs measure each spacer to determine the device's electrical performance as it is fabricated and predict end-of-line (EOL) performance.

Device makers use strain and stress technology to improve gate performance by etching a recess around the fully formed gate and using silicon germanium (SiGe) to put a strain on the gate. “The geometry of the recess is one of the primary drivers of final electrical performance,” McMillan said. Typical measurements include undercut (beneath the gate), depth and profile shape of the recess. The undercut is invisible when viewed from the top and down. While a CD-SEM can only see top-down, a 3-D AFM has been shown to measure undercut.

In many new device schemes, holes or lines are etched and then widened beneath the surface. For example, state-of-the-art DRAM technology uses a recessed transistor, where the transistor is under the silicon's surface and can be wider below the surface. Scatterometry uniquely enables these applications, although 3-D information is required.

Advanced Metrology Systems (Natick, Mass.) is working on an infrared (IR) metrology application for the measurement of metal film on the sidewalls of trenches. Michael Gostein, technology director for AMS, sees several applications: “One is copper damascene, in which a barrier film is put on trench sidewalls. Measuring thickness on such sidewalls has been problematic. Another similar, upcoming problem relates to finFETs, where the gate is wrapped around the channel. If metal gates are incorporated, the issue arises regarding the thickness of that metal film on the sidewalls, and how to measure it.” (Fig. 2 )

2. Sidewall metal thickness measurement using reflection of polarized radiation from a trench array. The dark arrows show direction of polarization, while the two-headed arrows show the di-rection of induced currents. Metal thickness can be determined from the polarized reflectance data. (Source: Advanced Metrology Systems)

AMS' proprietary approach uses a polarized IR beam to non-destructively measure metal and/or other conductive films on trenches. It is analogous to measuring the effective electrical resistance along and across the trench arrays. For example, with polarization across the trench array, sidewall thickness dominates the reflectance response, because electrical resistance is dominated by the thin sidewall “in series” with the thicker metal on the mesas and bottoms.

3. Example of the reentrant gate profile that is difficult to control with classic top-down metrology techniques. This type of structure requires metrology methods that are capable of determining the reentrant profiles with high precision. (Source: FEI Co.)

Even at 65 nm technology, fabs performing this experience process control difficulties, leading to excursions. “There's a challenge for top-down metrology, especially CD-SEMs, in being incapable to control this type of feature,” Stone said. If the model is correctly designed, scatterometry has a better chance. The problem is that it reveals whether things are good, bad or have changed, but not necessarily the problem's origin. Thus, it comes down to performing some sort of cross-section for validation, or revealing what happens on the gate with notching.

In BEOL profile metrology, with respect to metal lines and vias, fabs have tried to make as sloping a line as possible to improve barrier and seed deposition quality. Simultaneously, they are limited by the pitch of the particular process layer for how sloped they can get the sidewall. Shorting issues related to slope profile occur if the line has more slope; thus, as we progress through 65 and 45 nm to 32 nm, the drive is toward more vertical profiles for trench and metal layers.

Problems that arise with notching artifacts between interfacial layers — the intermetal dielectric (IMD) and etch stop — are mostly etch and clean control issues. The problems manifest as electromigration and device lifetime failures. Examining these with conventional top-down methods is difficult. Again, it drives the need for cross-sectional information.

David Scheiner, CTO of Nova Measuring Instruments Ltd. (Rehovoth, Israel), thinks SWA measurement has received less attention and exposure in roadmaps than CD measurements. “While sidewall angle measurements by CD-SEMs are challenged by high-aspect-ratio profiles, in most cases OCD [optical CD] systems provide a full profile for the 45 and 32 nm technology nodes,” he said.

SWA must be measured in two areas. The first is the patterning step of gate and spacers, where sidewall is measured for the control of source/drain (S/D) implantations and effective gate dimension. The second is during the development of the litho etch process, where a fast and reliable measurement of the focus/exposure matrix is needed. Parameters influencing sensitivity are optical material contrast and pattern density. The main challenge in using optical measurements lies in isolated periodic structures, where the total density of lines or holes is <10%.

There is no fundamental barrier for optical sidewall measurement on standard gate applications. Research is needed to increase the signal-to-noise ratio for better sensitivity, especially in low-density areas. For long-term needs, a quantum leap will be needed to break away from the ever-increasing complexity of optical solutions — moving to X-ray wavelengths, for example.

As dimensions shrink, there is a need to enhance the information content of OCD measurement techniques. Achieving this by system enhancement alone requires major development efforts. Contrariwise, with modern processes, there is a shift to variable multi-dimensional geometry applications. It is imperative to analyze the sensitivity of the various OCD system configurations to understand which are sufficiently sensitive and stable for the application. Advanced simulation will play an important role in process R&D to predict how process control needs can be met.

The next challenge facing metrology is in-die measurements on complex device structures. The need to measure the SWA is only part of a multifaceted problem involving complex geometry profiling and modeling, and electromagnetic field calculations in a multi-parameter environment.

Greg Wolf, director of new technology development at Rudolph Technologies (Flanders, N.J.), sees multiple sets of sidewall metrology applications, including OCD, for transparent applications, picosecond ultrasonics for metal-line-barrier applications, and the convergence of these technologies for metal gate applications. With OCD applications for spacers, for example, the challenge is to deliver the same precision previously achieved on flat test structures. In the context of gate sidewall spacers, there are no longer bulk materials in the sidewall spacer, because the demands of advanced node transistors require that all the films be graded materials, and rounding and tapering be engineered into the structures. “We've optimized our systems for these ultrathin sidewall applications,” he said.

In the context of metal lines, “There's picosecond ultrasonic technology. Its THz bandwidth gives a dynamic range of measurement spanning from thin to thick films, enabling the technique to measure barrier films deposited on the sidewalls of the trenches used to form metal lines,” Wolf said. While picosecond ultrasonics is commonly deployed to monitor line thickness in the chemical mechanical planarization (CMP) module, it can also monitor the barrier thickness in the empty trenches or on the sidewalls of the metal lines. In these measurements, the high-frequency portion of the spectrum gives the sidewall properties, and the low frequencies give line geometry.

SWA is important, because it is a specification not only on track performance, but also for overall litho. It affects post-etch CD transfer. If focus is out of spec, in extreme high-ratio features, it can also affect pattern collapse after development. Focus is a primary cause of SWA variation in litho tool and underlying film components. “This is obvious in isolated lines, the most sensitive to defocus, which makes them useful for monitoring,” said Anita Viswanathan, senior product marketing engineer at Tokyo Electron Ltd. (TEL, Austin, Texas). “However, on the track side, unless resist thicknesses are severely out of spec, this isn't the primary contributing factor to sidewall angle.”

Track-integrated scatterometry makes this data accessible. It is the enabler to view SWAs unobtainable from CD-SEM, especially in reentrant profiles. This helps fabs to determine and use optimal dose and focus conditions in a minimum of time, and immediately make adjustments without removing the wafer from the cell.

At the 65 nm node, integrated tools can characterize SWA for the pitches of con-cern. Although scatterometry's precision degrades as film thicknesses decrease, and line spacer ratios change as the signal-to-noise situation worsens, simulations reveal no issues at 45 nm. With scatterometry, there are no obstacles that cannot be met by light wavelength or polarization changes. The 32 nm node is still an open question as to what will be the SWA integrated metrology spec insofar as repeatability specs and sensitivity are concerned. This information will be useful for focus feedback. That being said, it is uncertain whether it would be used for APC feedback or as an excursion monitor. Track is considering the defocus impact on LWR, which worsens at 32 nm. Defocus degrades LWR at both low and high frequency; control from the perspective of pattern integrity as well as LWR will to come into play.

Merritt Funk, applications manager at TEL, sees the importance of SWA in etch specs increasing as we approach 32 nm. “For BEOL, trench is critical to maintain a SWA of 90° or less for a continuous seed layer coating. To ensure that the SWA does not go greater than 90°, the etched wafer spec becomes 88° or 89° to maintain a 90° or less spec across the wafer and over all the process variations; the closer to 90° the better for optimum conductive volume. Scatterometry for this application is perfect for feedback to monitor that the final etched profile does not exceed 90°.”

Apart from destructive methods, there is yet to be a practical sidewall measure-ment. The problem is that most destructive methods sample small areas, and the measurement does not represent what takes place. There are measurements where the sidewall is inferred from something happening someplace else in the structure — a significant metrology problem for thin films altogether. Metrology is needed at single-trench, almost point-level, to obtain the data. However, something that provides a better spatial average of what takes place across a number of devices is also needed.