Addressing Gate Leakage With Reengineered Silicon

The struggle to extend Moore's Law down the process curve has become a war of attrition. At lower nodes, the obstacles to continually improving performance while simultaneously reducing power consumption are formidable. Circuit dimensions have reached a point where basic material properties present major limitations, particularly below 65 nm.

Perhaps the greatest barrier to device scaling is gate leakage. As ICs migrate down the process curve below 65 nm, oxides that isolated transistor gates from their channels at earlier process nodes become too thin to perform that function. How bad is the problem? At 65 nm, leakage accounts for up to 40-50% of all power consumed, and that figure grows to 60-70% at the 45 nm node, with gate leakage being the dominant leakage mechanism in high-performance designs (Fig. 1 ). And, as manufacturers migrate further down the process roadmap, the problem is expected to exponentially increase.

Semiconductor manufacturers have tried a variety of techniques to extend the life of CMOS and lower power dissipation without changing materials or making large, new investments in manufacturing equipment or facilities. Many leading manufacturers, including IBM (Yorktown Heights, N.Y.), Intel (Santa Clara, Calif.), AMD (Sunnyvale, Calif.) and Toshiba (Tokyo), have used strained silicon approaches in recent IC designs. These methodologies slightly modify the normal inter-atomic distance between silicon atoms in the direction of conduction, which results in faster movement of electrons and holes through transistors. Two different approaches are commonly taken, as stretching (tensile strain) improves NMOS transistors, while compressive strain improves PMOS transistors. For NMOS, tiny silicon nitride “calipers” impart tensile strain, while SiGe regions regrown on either side of the PMOS transistors are literally used to squeeze out more performance.

1. Gate leakage accounts for up to 40-50% of all power consumed at the 65 nm generation, and that figure grows to 60-70% at the 45 nm node.

A number of issues are expected to arise, however, as manufacturers use strained silicon techniques at the 45 nm process node and below. First introduced at the 90 nm node, the technology's benefits begin to erode as channel lengths get shorter and shorter. For example, the drain current enhancement in strained NMOS devices reportedly saturates at 25%, regardless of which variant of strained silicon is used. Moreover, manufacturers will find applying the technology increasingly difficult to achieve as they move to smaller geometries and scale up stresses.

Enhancements such as hybrid-orientation techniques, used in conjunction with strained silicon, offer more promise for PMOS devices. But those approaches also face scaling issues. Finally, the amount of IC real estate devoted to the strain imparting stress-liner techniques will eventually begin to offset the area savings of moving to finer line geometries.

Some manufacturers have also addressed CMOS performance limitations by adopting silicon on insulator (SOI) approaches, which use an embedded oxide layer to isolate transistors from each other and, in the process, lower parasitic capacitance and reduce junction leakage. By placing a thin insulating layer between a thin layer of silicon and the silicon substrate, manufacturers reduce the amount of the electrical charge that the transistor has to move during a switching operation.

These approaches offer significant speed improvements in a highly compatible manufacturing process. Some manufacturers are also combining SOI substrates with strained silicon techniques to take advantage of both the performance enhancements SOI offers and the increased carrier mobility of strained silicon. But SOI techniques also present some challenging yield problems at finer process nodes, as well as thermal resistance issues that could force ICs to run at higher operating temperatures. More importantly, neither strained silicon nor SOI solve the intrinsic gate leakage issues manufacturers are now facing.

Other alternatives proposed by the International Technology Roadmap for Semiconductors (ITRS) reduce gate leakage using high-k dielectric oxides, which provide better insulation, in conjunction with gates made out of more conductive metals. While researchers have made significant progress with high-k dielectrics, problems persist with Fermi-level pinning and its resultant generation of higher threshold voltages, mobility degradation and reliability problems.

Advances have also occurred in the integration of metal gates into CMOS devices to reduce power dissipation. Approaches such as the full silicidation of polysilicon gates (FUSI) offer a number of attractive advantages, including compatibility with mainstream polysilicide front-end processing and the ability to use ion implantation for work function tuning. But scalability issues persist, and the introduction of a new material into the silicon manufacturing process presents significant cost issues. Given these risks, most manufacturers have opted to delay introduction of high-k or metal gates at the 65 nm node.

What silicon manufacturers clearly require is a new methodology capable of altering the properties of the silicon to improve power efficiency and transistor performance while maintaining compatibility with standard CMOS manufacturing equipment. That breakthrough would allow manufacturers to continue to pursue their aggressive roadmaps while still leveraging their existing manufacturing infrastructure and the cost benefits that go with it.

To address this challenge, we have developed a new approach that promises to extend the historical benefits of CMOS manufacturing techniques to 45 nm and below without disrupting the semiconductor industry's existing manufacturing infrastructure. This new process, called the MST platform, is designed to dramatically reduce gate leakage, and thereby power consumption, while enhancing drive current.

This so-called “silicon-on-silicon” approach relies on a form of band engineering within the silicon to achieve these results. But instead of significant changes in the energy bandgap, this technology relies on alterations to the overall band curvature that result in a modified effective mass. Developed over a five-year period by our team, in conjunction with the Advanced Technology Development Facility (ATDF, Austin, Texas) and the Lawrence Semiconductor Research Laboratory Inc. (LSRL, Tempe, Ariz.), the company's techniques are a direct outgrowth of its extensive background in the quantum mechanics of deep submicron devices.

Researchers began with two fundamental observations. First, the electronic properties of any material are primarily governed by its band structure or the relationship between the energy and momentum (speed) of electrons and holes in the material. The band structure of any material is a function of the arrangement of the atoms, referred to as the lattice, and the electronic nature of the atoms themselves.

Secondly, the larger the curvature of a material's band minima and maxima, the more easily electrons are accelerated with an applied electric field. Together, the ease of acceleration and the scattering effect electrons encounter determine how much current flows as the result of an applied voltage. Therefore, the larger the curvature, the more current that can be driven.

To reengineer the silicon and improve performance, the developers had to modify the lattice of the atoms. But instead of changing the structure of the lattice in the plane of the device (as is done in strain techniques) — which one might assume would be required to improve performance — they discovered that they could manipulate the bands in a planar silicon device by breaking the periodicity in the vertical direction. Moreover, by taking advantage of recent advances in manufacturing equipment and the ability to build up silicon by individual atomic layers, this could be achieved with a conventional epitaxial process step.

2. Electron density stratification as a result of the insertion of a non-semiconductor layer during silicon epitaxy.

At the same time, the introduction of this “superlattice” layer provides better blocking of the vertical conduction between the gate and channel. Since this material is anisotropic, it provides higher effective mass (the band curvature is reduced) and lower conductivity in the vertical direction. That lower conductivity contributes to lower gate leakage.

The technology has been validated by industry standard e-test and bench measurements on test die run on more than 1000 wafers. Initial trials indicated that the new technology will reduce gate leakage by up to 60% in NMOS transistors and up to 80% in PMOS transistors, while increasing drive current in the channel. In its current form, this technology is initially being targeted at 65 and 45 nm processes. But given its simple adaptability to the existing CMOS infrastructure and its ability to reduce gate leakage and simultaneously enhance mobility, this new technology will clearly enable low-power and high-performance 32 nm development (Fig. 3 ).

3. Reduction in inversion gate leakage for a typical plasma nitrided oxide gate oxide process.

Looking ahead, the technology's ability to manipulate the electronic properties of silicon promises to have additional applicability as manufacturers move to high-k/metal gate processes. Over the longer term, as semiconductor manufacturers move to 3-D architectures and finFETs, this new approach, with modest modifications in an epi step, could be designed to wrap around a fin in a finFET and support lower leakage power in 3-D IC designs.

Implementing the technology only requires a few simple additional steps to a standard CMOS flow. Unlike other approaches, the MST platform does not require the introduction of risky new materials. Instead, it relies on a simple modification in the methodology used to construct the transistor channel. Manufacturers using this technology simply insert epitaxially grown silicon into their standard CMOS flow as a channel replacement layer.

To illustrate its compatibility with existing tooling, the modified epitaxial process required for deposition of the channel replacement layer was initially developed on an industry-standard ASM 2000 reactor. The channel replacement layer was then inserted prior to gate processing.

As a result, the implementation of this new platform requires no new tooling. It has been designed from the ground up to be fully compatible with manufacturers' baseline processes, whether they are using bulk CMOS, strained silicon or SOI.

Furthermore, semiconductor manufacturers can implement this new process at virtually no additional cost. Savings from both die real estate and the use of existing tooling are expected to make the “silicon-on-silicon” methodology close to cost-neutral. Cost models that include wafer and die yield analysis show that production cost break-even is achievable with modest circuit-specific layout reduction. For example, designers fabricating a typical driver circuit using larger, non-minimum geometry transistors can use this process and its enhanced current driving capability to reduce transistor width and achieve significant die area savings.

After four decades, the electronic industry's seemingly reliable ability to double silicon performance by reducing circuit dimensions every two years is in doubt. Basic materials properties appear to have reached their limits, and gate leakage loss presents a formidable challenge to future advances in process technology. While manufacturers have adopted a variety of innovative approaches — from strained silicon and SOI to high-k/gate materials — to address bulk CMOS limitations, none sufficiently address the gate leakage problem. By reengineering the basic silicon channel technology using band-engineering techniques, a new silicon-on-silicon process promises to dramatically reduce gate leakage in standard CMOS processes without introducing disruptive new materials or substantially altering the standard CMOS manufacturing flow.