Reaching a Consensus of Challenges

As an industry, we are used to change. However, each succeeding node is coming at us at a higher warp speed than the one preceding it. Nowhere in the various sectors of semiconductor production is this truer than for metrology, and the fact that some of the problems speeding our way seem to require an engineering development rather than a R&D solution does not make them any less critical.

It appears to be an open question as to whether CD-SEM and scatterometry are extendable through the 22 nm node. Among many other challenges is linewidth roughness (LWR) — linewidths are getting so narrow that any sort of LWR becomes more significant and difficulties multiply when attempting to ascertain a true linewidth. It remains to be determined how scatterometry will deal with line edge roughness (LER) and LWR. Presently, scatterometry provides an average picture of linewidth without LWR information. Although there are some ideas on how to cope with the situation, none seem to have gotten very far.

Overlay is another boogeyman. Overlay measurement needs will be very demanding, particularly in view of the kind of lithography expected to be in use at the 22 nm node — it should considerably impact overlay requirements. Will companies be able to use double patterning and immersion lithography, or have to switch to extreme ultraviolet (EUV)? The lithography researchers must provide the necessary background to orient the metrology community’s effort. Double patterning requirements (or some similar litho trick such as double exposure) will seriously challenge metrology, particularly if litho is still optical at the 22 nm node. In any case, litho process control is key.

Another consideration is the 3-D nature of novel structures. The implementation of 3-D interconnect is taking place, and while not exactly “nanoscopic,” it contributes unsolved metrology challenges. We must understand what and how diverse the challenges are, but for this we must know what 3-D interconnect approaches are being seriously considered, and whether there is sufficient common ground to begin doing metrology equipment development. In terms of 3-D structures in transistors, will finFETs or something like that be used? How do we do CD and sidewall measurements of finFETs? In R&D, key requirements are tied to the measurement of features on sidewalls — an as yet unmet need.

Stress metrology was never simple, and as things increasingly become nano, it is not getting any easier. There are always the problems of what the significance of a local stress measurement is, and what to do for it. When one does TEM analysis using something like convergent beam electron diffraction and determines strain, and strain and stress are interrelated, there is always the question of how stress measured in a cross-section relates to the stress in a real device. For R&D, more material characterization could be done employing some of these advanced microscopies’ cross-sections, but once into manufacturing, less destructive process control methods are needed.

Beyond CMOS, some are considering alternatives such as spintronics. However, spintronics, as discussed in the literature, operates at ~5K and, in a practical sense, it is almost miraculous to do measurements at that temperature. For technologies like nanoelectronics and molecular electronics to leave the lab, different measurement capabilities will be needed, mostly characterization measurements.

This month, the result of work aimed at understanding some of these measurement needs will be presented at the 2007 International Conference on Frontiers of Characterization and Metrology for Nanoelectronics , as well as a glimpse of measurement technologies that may be needed beyond 22 nm toward the beyond-CMOS era. Presentations will examine some of these hurdles and barriers, and suggest possible solutions for several of these uncharted areas. Some of this work will hopefully make us more efficient when many of these technologies do come to fruition in the beyond-CMOS era.

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