Silicon Scaling: Future Directions

For the sake of brevity, let's just look at the challenges in low-power portable technologies that are driving the bulk of volumes today. International Data Corp. (IDC, Framingham, Mass.) forecasted correctly last July that close to 1 billion cell phones would be shipped in 2006. Those volumes, combined with the changing tastes of consumers in terms of feature sets, are placing incredible demands on consumer electronics manufacturers. Adding video and digital music to almost every conceivable form factor is only increasing design complexities, and cycle times are short because consumer preferences constantly evolve.

To maintain affordability for the users and profitability for the manufacturers, scaling the silicon area in these products is as critical as ever. Scaling to reduce silicon production cost is a double-edge sword, however (Just ask any chip manufacturer that has bought an immersion scanner). Transistors that leak power as they get smaller only compound the problems associated with supplying the battery-powered portable electronics market.

For the industry, these challenges offer tremendous opportunity for innovation in the semiconductor equipment space and in IC design and manufacturing. Resolution enhancement technology (RET) and the exploration of new immersion fluid options are vital to staying on the design rule scaling roadmap. Power management is another area for circuit, architectural and process innovation. Ironically, making the transistors smaller causes them to leak power. However, having more transistors gives us more flexibility in a given area of silicon. This is the basis for chips with multiple processor cores, and massive parallelism in instruction execution within each processor and across multiple processors. This has long been the domain of micro- and digital signal processors. As we move forward, these approaches are finding their way into consumer ICs.

Numerous other innovative techniques have been developed to leverage available transistors to adjust functions dynamically and still achieve desired performance. These techniques span the entire spectrum of design from devices and circuits to testability and software/system control mechanisms. Static and dynamic body biases and voltage vs. frequency control mechanisms, as well as various fundamental architectural techniques to manage power, are all being implemented in various ways today.

For transistor performance gain and current leakage minimization, a menu of transistor choices is available to designers — multiple threshold voltages, double or triple gate oxide thicknesses and standard cell libraries with different gate lengths. The judicious use of these transistor choices at the sub-chip level results in the highest performance and lowest power consumption for the entire chip.

We are also seeing high-k and metal gate introduction announcements for microprocessor manufacturing at the 45 nm node. There is still room for silicon oxynitride scaling in low-power consumer electronics manufacturing, and new gate materials are likely to appear only after the technology is more mature and cost-effective. Because there still exists a lack of consensus on metal gate materials or an integration approach, this poses a significant cost barrier for equipment companies, and is a major cost-adder for IC companies. I expect a few companies to make the move regardless of cost (and perhaps pay the price in terms of R&D cost and yield/reliability), while others will wait until the technology is more mature.

Interconnect innovation has few such material opportunities on the horizon. Copper is it for the foreseeable future. Lower-k dielectrics come with increasing porosity and lower material strength. There are two solutions in the industry. One approach is to use highly porous spin-on low-k materials sandwiched between thicker, more rigid dielectric films, while the other involves evolutionary changes to the low-k material, with aggressive reduction in the thickness of liners and capping layers. Both approaches have their risks and challenges, with incrementally small benefits at best. At this point, reliability risks mostly outweigh the benefits, so small evolutionary changes are more likely.

There are many opportunities for reducing and/or optimizing device variability on advanced nodes. In the past, the focus has been on reducing variability (in critical linewidths, layout styles, thicknesses, dopant levels, etc.) in the fabs. While this focus continues, there is a clear recognition that chip functionality and yields are ensured when designers also comprehend variability during circuit design and layout. In the past few years, an entire industry has emerged around the topic of design for manufacturing (DFM). It reminds me of the early days of yield management software packages in the mid-90s. Many started the race, but only a few finished! The winners were those that were successful in making their software packages work smoothly with existing manufacturing and design systems and EDA tools.

Solving these universal problems is changing the shape of the industry, promising a year ahead that will be exciting, even more so than usual, as we move out of adolescence and into middle age. Let's mature gracefully.