High-k/Metal Gate Announcements?

Intel's and IBM's recent announcements that they will be employing hafnium-based dielectrics and metal gates into their 45 nm production products were remarkable in several respects — because they imply the end of an era with polysilicon and oxide-based gates — and because there was very little technical detail supporting the claims.
 
Often, such announcements have been tied to the release of a technical paper showing “proof of concept” that, at least at the device level, a given solution is available. This was the case when Tahir Ghani, IBM fellow, presented the proof that strained silicon solutions could be successfully integrated into an engineered solution in 2003, as reported in IEDM Technical Digest. This paper is often cited as the indicator that strained silicon techniques would be used in manufacturing by a variety of companies.

In contrast, while both Intel and IBM have published papers on high-k and metal gates, it is unclear what solution these companies will definitely be using in their production lines (by some time in 2008). The answer is neither straightforward nor apparent.

In fact, if you look at the latest International Technology Roadmap for Semiconductors (ITRS) update , it indicates that high-k dielectrics and metal gate materials have been delayed from production in 2008 to 2010. IBM and Intel, of course, are two important contributors to the roadmap. You can judge for yourself what this does to the value of the roadmap.

However, we can surmise some things from recent activities. IMEC, which has core partnerships with Infineon, Intel, Matsushita/Panasonic, Philips, Samsung, STMicroelectronics, Texas Instruments, TSMC and Micron, has proven the concept of FUSI metal gates (fully silicided polysilicon by nickel) on HfSiON dielectrics, with both high and low threshold voltages, making this combination a candidate for low-power and high-performance applications. But not everyone has followed the development path of FUSI, with the exception of Texas Instruments. In fact, Intel said it is using two different metals for the pFET and nFET, meaning FUSI is out. Freescale did not follow the development path for FUSI, and it is likely that IBM, though it certainly investigated FUSI, may have diverted development dollars to two different metal electrodes some time ago as well.

Because IBM and Intel are both emphasizing compatibility with existing CMOS processes, it also seems likely that a replacement gate strategy (with substantial added cost and complexity) has not become necessary, and a gate-first approach, with associated high-temperature thermal annealing cycles, has been retained. It appears that HfSiON offers a more manufacturable solution than HfO₂, because HfO₂ is incompatible with source/drain activation temperatures. In addition, HfSiON/SiON gives a thinner effective oxide thickness than HfSiON/SiO₂. Freescale has published very good results using HfZrO_x. HfLaON, although not widely covered, is also possible. Or lanthanum can be used as a dopant to reduce effective oxide thickness.

That leaves the pFET and nFET metal gate selection. The nFET has proven to be a little less challenging, although stacks involving TaN, TiN, tungsten, TaSiN and TiC metals are all being tested and combined with various dielectrics. Among the numerous combinations, the stack W/TiN/HfSi_x/SiO₂ looks promising, and it can provide a comparable work function to that of n+ polysilicon. For the pFET, W/TiN/HfO₂ may also work, allowing device manufacturers to stick with tried-and-true materials like tungsten and titanium. However, this approach seems to work best in a damascene, gate-last approach.

Another possibility is TiN/TaN/HfO₂. The pFET metal is the more problematic to optimize, owing to threshold voltage roll-off with scaled dielectrics, according to Sematech and others. In addition, compatibility with the compressively stressed embedded SiGe source/drain is likely, so the gate must be protected from germanium using a GeC buffer layer or other approach. A relative newcomer, molybdenum-based pFET stacks in a metal-inserted poly stack can be performed as a gate-first process (MoO_x/HfSiON or MoO_x/SiON). In fact, other metal-inserted approaches with poly/TaN/HfSiON or poly/TaN/SiO₂ look very promising.

Still, with the enormous advancements that have taken place in strain engineering (see “Strained Silicon: Essential for 45 nm ”), clearly the lower-cost, low-complexity approach involves everything but high-k and metal gates, if the change can be avoided. If a well-engineered solution exists with poly/SiO₂, high-k and metal gate will wait.