Hot Spot Cooling
Embedded thermoelectric coolers, fabricated with a nano-structured thermoelectric thin film, can provide site-specific cooling to eliminate hot spots.
Bob Conner, Nextreme Thermal Solutions, Research Triangle Park, N.C. -- Semiconductor International, 2/1/2007
Total heat dissipation is being driven upward with continued CMOS scaling caused by increasing dynamic power dissipation plus increasing leakage power dissipation.¹ Dynamic power dissipation, resulting from voltage transitions as transistors turn on and off, is given by:
Pdynamic=α C V² fclock
where α is the percentage of transistors switching at a given time, C is the total capacitance, V is the supply voltage, and fclock is the operating frequency.
Dynamic power dissipation is driven upward by integrating more circuits on the chip (increasing total capacitance) and increasing their operating speed. The rate of increase has been offset by decreasing the supply voltage (from 5 to <1 V) and reduced capacitance of the individual transistor over the past 15 years, as CMOS technology scaled from micron-scale to nanometer-scale feature sizes. However, as CMOS is scaled from 90 to 32 nm, there’s little room to further decrease supply voltage in order to reduce dynamic power dissipation. The result is that heat dissipation for high-end CPUs is forecast to increase to 200 W, as both the number of transistors per chip (from 553 to 1106 M) and the on-chip local clock double (from 6.8 to 12.4 GHz).²
Leakage power dissipation is caused by current leaking through the transistors, even when they are turned off. The two major contributors to leakage power are gate leakage — a tunneling current through the gate oxide — and subthreshold leakage — a weak inversion current across the device. High-k dielectrics are expected to mitigate the gate leakage. Subthreshold leakage, which is exponentially dependent on temperature, can be reduced by decreasing temperature or increasing the threshold voltage — with the trade-off of reduced operating speed. Small transistors leak more than large ones. As CMOS is scaled to smaller gate lengths, leakage power is forecast to exceed dynamic power dissipation.³
Effects of temperature
Temperature affects the performance, leakage power and reliability of an IC. Chip performance degrades as temperature increases, since current (hence speed) decreases exponentially with temperature. Resistance and threshold voltage vary with temperature. Local temperature variations cause signal integrity and timing issues. As clock speed increases, the transistors become more sensitive to temperature. As discussed above, subthreshold leakage increases exponentially as temperature is increased. Thermal runaway results from an increase in temperature, causing increased leakage power and resulting in self-heating, which further increases temperature. It is generally found that product reliability degrades exponentially as temperature is increased, following an Arrhenius relation for mean time to failure. For many technologies, an increase of 10-15°C can reduce chip lifetime by >50%.
Non-uniform power dissipation
Localized areas of high-heat flux are becoming more pronounced as process technology is further scaled and total power dissipation increases. These localized high-heat flux areas create hot spots, which are significantly above the average die temperature. Hot spots limit the IC’s performance, reliability and yield, which are all very sensitive to small changes in temperature.
Hot spots are a growing problem in a variety of high-performance CMOS ICs. In these chips, the close proximity between transistors to reduce “time of flight” delays within a single functional block. Close packing of these high-performance circuits results in high-heat fluxes, since power is dissipated by both the transistors and their interconnects. Moreover, the disparities in local heat flux are enhanced by the placement of core processors that dissipate a significant amount of power in close proximity to cache memory, which dissipate little power. Compounding this non-uniform power dissipation problem is the integration of multiple processor cores per die. It has been reported that cooling hot spots could produce speed gains of 30-200% in some CMOS processors.4
Thermoelectric cooling
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| 1. A thermoelectric cooler works by the Peltier effect — the creation of a heat difference when a current is passed through two semiconductors. |
TECs have traditionally been fabricated using thermoelectric pellets (typical dimensions of 1 mm³) assembled into a large array of elements between two ceramic substrates.
An embedded thermoelectric cooler (eTEC, Fig. 2 ) is a miniature, solid-state heat pump fabricated with nano-structured thermoelectric thin film using semiconductor processing techniques. eTECs cool hot spots on ICs by pumping heat from low thermal conductivity materials (the die and thermal interface material [TIM]) to a high thermal conductivity material (a heat spreader). Cooling hot spots increases product performance, reliability and yield and reduces cost by simplifying “downstream,” uniform chip-cooling components.
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| 2. An embedded thermoelectric cooler cools hot spots by pumping heat from the die to the heat spreader. |
eTECs can operate in a high coefficient of performance (COP) regime; COP is a measure of efficiency defined as cooling power divided by input power; while maintaining a reasonably high-heat flux (50–100 W/cm²). To cool a 4 W hot spot, an eTEC with a COP of 2.0 would only need 2 W of input power.
eTEC’s solid-state design (no moving parts or fluids) provides high reliability. The eTEC’s small footprint (typically a few millimeters per side) enables site-specific spot cooling. Focusing the cooling just on the hot spots reduces the overall amount of heat removed from the chip, as the eTEC does not pump heat from the “background” (i.e., areas of the chip with temperatures well below the junction temperature).
Reducing the hot spot temperature with a uniform chip-cooling solution — TIMs, heat spreaders, heat pipes, cold plates, heat sinks or fans — is inefficient, because cooling the rest of the chip is unnecessary and requires a larger heat sink and/or faster fan speed. An example of reducing hot spot temperature by decreasing the heat sink thermal resistance is shown in Figures 3 and 4 .
The most efficient way to reduce the temperature of hot spots is to locally cool only the high-heat flux areas, since this approach avoids overcooling of the adjacent silicon. An eTEC cooling a hot spot in a flip-chip packaged CMOS IC is shown in Figure 3 . The active side of the die is faced down toward the substrate. Some of the heat flows through the solder balls to the substrate. Most of the heat flows through the backside of the die, the first thermal interface material (TIM1), the heat spreader (which forms the lid of the package), the second thermal interface material (TIM2), and finally through the heat sink to ambient. The hot side of the eTEC is soldered to the heat spreader, providing an excellent thermal interface. The same TIM1 that is used between the die and heat spreader is used to interface the die to the eTEC’s cold side.
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| 3. Most of the heat flows out the backside of the die, through the thermal interface material (TIM1), heat spreader, TIM2 and the heat sink, to the ambient. |
Figure 4 illustrates how the eTEC reduces junction temperature for a given die heat dissipation (qdie) by creating a temperature inversion between the TIM1 and heat spreader. The Y axis depicts the thermal driving force (Tjunction-Tambient). This value is limited to ~50-60°C, because the junction temperature (Tjunction) must be kept below ~90-100°C for CMOS ICs, and the ambient temperature (Tambient), which is typically ~40°C, is being driven up as increasing integration and shrinking system footprints force designers to dissipate more heat in a smaller volume. The X axis represents the thermal resistance of each component in the thermal stack. The total thermal resistance (Rthermal) to the heat flow, responsible for the (Tjunction-Tambient) temperature rise, is typically broken down as follows: 40-45% from the heat sink thermal resistance (Rsink); 40-45% from the IC package, (which is the thermal resistance of die plus TIM1 plus heat spreader (Rdie+RTIM1+Rspreader)); and 10-15% from the TIM2 thermal resistance (RTIM2).
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| 4. The eTEC reduces temperature inside the package where it matters most, while elevating the case and heat sink temperatures slightly. |
The slope of the line is the heat transfer rate:
q=( Tjunction-Tambient)/(Rthermal)
which is analogous to the flow of electric current through a conductor (I=ΔV/Relectrical), where the temperature difference is analogous to V (voltage difference) and q (heat transfer rate) is analogous to I (current). Without an eTEC, a larger heat sink and/or faster fan speed, which are very undesirable in most applications, is required to reduce Rsink to decrease the hot spot temperature (shifting the red line down in Fig. 4 ).
The eTEC reduces the temperature at the TIM1-to-heat spreader interface (Fig. 4 ). The amount of heat transferred from the die to the TIM1 is the same as for the no eTEC case (Note that the slope of the red and green lines at the die and TIM1 are the same). Since the power input into the eTEC (PeTEC) must be dissipated, the amount of heat transfer from the spreader to ambient is higher (The slope of the green line is higher than the red line). The eTEC serves as a heat pump to move heat from the IC and TIM1, which have a low thermal conductivity, to the heat spreader, which has a high thermal conductivity. The temperatures inside the IC package are reduced where it matters most, while the temperature of the case and heat sink increase by a very modest amount. This temperature change is proportional to the fractional increase in total dissipated package power resulting from the operation of the eTEC, and can be expected to fall 2-3% when the eTEC is used to cool a small hot spot.
eTECs are optimized for non-uniform cooling to complement uniform cooling solutions (e.g., TIMs, heat spreaders, heat pipes and heat sinks). eTECs fit well into existing packaging methodologies and extend the life of current uniform cooling thermal management solutions. When used in conjunction with emerging thermal management solutions, such as liquid microchannel coolers, considerable volume and weight savings can be achieved. eTECs are optimized for non-uniform cooling and complement uniform chip-cooling approaches to reduce the temperature of hot spots, increase chip performance, and improve yield and reliability.
Hot spots, resulting from localized areas of high-heat flux on an IC, significantly increase a package’s thermal resistance, limiting chip performance, reliability and yield. They are a growing problem in microprocessors, graphics processors, ASICs and other high-performance CMOS ICs. eTECs, fabricated with a nano-structured thermoelectric thin film, can be unobtrusively integrated close to the heat source. Their small size, high cooling flux capability, and high efficiency enable site-specific cooling of hot spots.
| Author Information |
| Bob Conner is the vice president of marketing and business development for Nextreme Thermal Solutions . He has held many roles in the microelectronics industry, including CEO of Symmorphix and managing director of corporate marketing for AKT (a joint venture between Applied Materials and Komatsu). Conner has an MBA from the University of Chicago and a B.S. in mechanical engineering and materials science from Duke (Durham, N.C.). |
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